Electronics Assembly Knowledge, Vision & Wisdom
Board Level Failure Analysis Demount Challenges Package Package
Board Level Failure Analysis Demount Challenges Package Package
Board level FA and component demount experiments for PoP mounted on PCB is discussed. The FA methods includes 2D and 3D X-ray imaging, cross section and DnP test.
Analysis Lab

Analysis Lab programs cover topics including:
Corrosion, Contamination, Data Acquisition, ESD and EOS, Inspection, Measurement, Profiling, Reliability, R&D, RFID, Solder Defects, Test, Tombstoning, X-ray and more.
Submit A Comment
Comments are reviewed prior to posting. You must include your full name to have your comments posted. We will not post your email address.

Your Name

Your Company

Your E-mail

Your Country

Your Comment

Authored By:
Shu Lee Lim and Priyanka Dobriyal
Intel Corporation
1Kulim, Malaysia, Hillsboro, OR, USA

The demand to build products using Package on Package (PoP) technology is increasing rapidly especially for handheld products such as mobile communications, tablet and camera based technology. Generally, PoP is an integrated circuit packaging that vertically combine discrete logic and memory ball grid array (BGA) packages. It is different from traditional packaging whereby each die is placed in its own package and mounted directly on the printed circuit board (PCB) side-by-side. The main driving force for PoP development is to allow higher component density in devices as the PoP structure promotes space saving. This packaging also leads to better electrical performance as there are shorter path for communication between microprocessor and memory. However, the board level failure analysis (FA) becomes more challenging when the packaging technology transits from traditional packaging to PoP packaging.

For instance, the multiple interfaces of PoP packaging hinders the dye and pull (DnP) test at a selectively interface for solder joint evaluation. Other methods such as 2D X-ray imaging could only provide preliminary indication of the gross defect. To-date, there are limited works being documented for board level FA for PoP component mounted on PCB. Moreover, underfill is sometimes applied to the PoP packaging to enhance the reliability of the product. With the introduction of underfill, conventional thermal method to demount component for fault isolation or component testing creates another challenge. Hence it is highly desirable to streamline the methodologies to address these challenges for better root cause analysis. This paper discusses about the board level FA and component demount experiments for PoP mounted on PCB. The FA methods includes 2D and 3D X-ray imaging, cross section and DnP test. PoP component demounting from board and its challenges are also discussed in this paper. The demount methods cover thermal, mechanical milling and micro-abrasion technique.

In our work, various board level FA methodologies for PoP assembled on boards were evaluated. The result showed 3D X-ray imaging can overcome the limitation of 2D X-ray imaging in detecting the anomalies of multilayer solder joints in the non-destructive way. 3D X-ray imaging technique demonstrated its capability in isolating the defect down to specific stacking of PoP component mounted on board which is very useful for further failure mechanism investigation using destructive analysis method. Cross section method had also been proven to be one of the destructive FA technique for the root cause analysis of PoP component assembled on board.

On the other hand, DnP method is not recommended for stack by stack solder joint evaluation of PoP as the component breakage tends to happen at weaker interface of the stacking instead of intended interface during pulling process. For underfill PoP demount, combination of mechanical milling and autolapping process had showed a promising result. Microabrasion techniques using walnut shell can be used for excessive underfill cleaning post demount process. Whereas thermal method is not able to demount the underfill PoP as underfill material did not melt at reflow temperature as how solder behaves. Furthermore twisting force applied during component pick up at reflow temperature potentially damage the PoP component.

Initially Published in the SMTA Proceedings

No comments have been submitted to date.
Free Newsletter Subscription
Every issue of the Circuit Insight email newsletter will bring you the latest information on the issues affecting you and your company.

Insert Your Email Address

Directory Search

Program Search
Related Programs
bullet Can a CTE Mismatch Cause Reliability Problems?
bullet Challenges on ENEPIG Finished PCBs
bullet Effect of Assembly Pitch and Distance on Solder Joint Thermal Cycling Life
bullet Insertion Loss Comparisons of High Frequency PCBs
bullet Realization of a New Concept for Power Chip Embedding
bullet Help With Lead to Hole Ratio
bullet Influence of Copper Conductor Surface Treatment for High Frequency PCB
bullet V-Score and Depanel in One Step
bullet BTC-QFN Test Board Design for Qualifying Soldering Materials
bullet Board Level Failure Analysis Demount Challenges Package Package
More Related Programs