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Void Reduction Method for BTC Using Exposed Via in Pad
Void Reduction Method for BTC Using Exposed Via in Pad
The method explored in this paper regards the use of exposed via in pad. A dedicated test vehicle was designed for two types of QFN components.
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Authored By:
Alfredo Garcia, Domingo Vazquez, Ricardo Macias, Rodrigo Ibarra, Mulugeta Abtew, Iulia Muntele

Joe Smetana2

Void reduction strategies used with different levels of success throughout the industry include managing reflow profile parameters, solder paste deposit volume and solder paste type, stencil aperture cut to different geometries, thermal pad geometries with and without solder mask webs, vacuum assisted reflow, sweep stimulation of PCB substrate, use of solder preforms, tinning of the components pads prior to placement and reflow, I/O aperture design to overprint at the toe of the pad, and exposed via in pad [1-8]. Translation of these methods and their combinations for void control on the thermal pad of bottom terminated components (BTC) has met with different levels of success in volume production.

The method explored in this paper regards the use of exposed via in pad. A dedicated test vehicle was designed for two types of QFN components. The main variables taken into account were the component size, number of exposed via in the thermal pad, via pitch, via size, and solder paste coverage. The responses sought in this experiment include thermal pad void level and solder wicking down the via barrel with resulting solder protrusion on the opposite side of the PCB.

The results indicated that solder will wick down the exposed via in pad regardless of the via diameter and solder paste coverage. Despite this finding, there were no defects recorded like component tilting, skewing, opens, or solder bridging. Specific configurations attained voiding levels in the thermal pad below 25%; however, other configurations did show void level for the thermal pad up to 50%. A discussion will be presented regarding the effect of the board thickness and the geometry of the via array on the thermal pad solder coverage and voiding level.

A test board was designed to test an isolated set of conditions for void reduction on the thermal pad of QFN. The hypothesis that a small enough via diameter would prevent molten solder from wicking in the via while allowing volatiles to escape and facilitate void reduction was limited to three finished TH via diameters: 0.00787”, 0.009” and 0.0098”. Only a narrow set of parameters displayed a reduced void%, and limited the wicking of solder inside the via.

Initially Published in the SMTA Proceedings

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