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Effect of Package Warpage and Composite CTE on Failure Modes
Effect of Package Warpage and Composite CTE on Failure Modes
This paper gives examples of the BLR TC failure modes and locations of package test vehicles designed to correlate failure modes.
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Authored By:
Andrew Mawer, Paul Galles, Mollie Benson and Burt Carpenter
NXP Semiconductors, Austin, Texas USA

Neil Hubble
Akrometrix, Atlanta, Georgia USA

Increasingly, demonstrating adequate reliability performance for a given packaged integrated circuit (IC) while mounted to a printed circuit board (PCB) that represents as closely as possible the final application is a requirement from both IC suppliers themselves and their Tier 1 customers. This combined with the ongoing miniaturization of electronic packages in both footprint and height, sometimes to the detriment of board-level reliability (BLR) thermal cycling (TC) performance, has put more scrutiny on the robustness of the interconnection from the package to the PCB. Well known byproducts of miniaturization that can lead to decreased solder joint interconnect fatigue lifetimes in BLR TC on BGAs, for example, include finer pitches with smaller solder spheres, larger die to package ratios and thinner laminate substrates. Not only is the fatigue lifetime in BLR TC examined closely, but also the specific failure modes and location. Additionally, depopulation of certain BGA locations to facilitate package substrate or PCB routing can affect BLR cycles to failure and influence the location of first failure.

This paper will give examples of the BLR TC failure modes and locations of various package test vehicles that were designed to attempt to correlate those failure modes to the in plane CTE and out of plane warpage behavior of those packages. BLR TC results will be presented in Weibull format along with failure analysis using both cross-sectioning and dye penetrant analysis.

Package CTEs were measured using Digital Image Correlation (DIC) and package warpage over approximately the same temperature range as TC was measured using CoolMoire, a Shadow Moiré technique that brings the sample to temperatures as low as -55 degrees C. The results show that by knowing both the warpage and CTE behavior of packages, the board mounted TC failure location, and to lesser extent, the relative performance, can be better understood. The two package types that will be studied are flip chip PBGA (FC PBGAs) and overmolded, wire-bonded PBGAs with various die sizes.

Table 2 summarizes the observations for each part type after reviewing all the BLR solder joint failure locations in thermal cycling and correlating these failure locations to the in plane resolution and provide automatic ordering of the interference fringes. This technique is implemented by vertically translating the sample relative to the grating. In this case, a convective cooling module is added to the shadow moiré system to enable sub-room temperature readings. The resulting technique is called CoolMoiré. For the above room temperature portion of the BLR thermal cycle, convective heating is used to heat the sample.

Initially Published in the SMTA Proceedings

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