Electronics Assembly Knowledge, Vision & Wisdom
Hi Pot Dielectic Breakdown
Hi Pot Dielectic Breakdown
How the Electrical Test industry combats requirements and provides solutions to adhere to ever changing requirements is discussed.
Materials Tech

Materials Tech programs cover topics including:
Adhesives, Chemicals, Cleaning Solutions, Coatings, Components, Design, Embedded Technology, Fasteners, Finishes, Flex Circuits, Flip Chip, Fluxes, PC Fab, Solders, Solder Masks, Solder Paste and more.
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Authored By:
Todd L Kolmodin, VP Quality
Gardien Services USA Inc,
Forest Grove, Oregon USA

Summary
The Printed Circuit Board (PCB) builds get ever more complex. With this the layer counts climb but the overall thickness remains the same. From this the cores of the build are reduced and the dielectric layers are reduced. When this happens there are more concerns regarding how these stack-ups can withstand higher voltage with the thinner cores. OEMs are making stronger requirements regarding dielectric withstanding. This paper will outline how the Electrical Test industry combats these requirements and provides solutions to adhere to these ever changing requirements. IPC states methods, ie TM-650 and IPC-6012 but these are guidelines. This paper will elaborate around these requirements regarding Condition A and Condition B from the TM-650 specification.

The paper will also outline the opportunities around testing Dielectric Breakdown or HiPot. The paper will outline:
HiPot Manual Testing HiPot Fixture Assisted Testing HiPot Full Automation Testing Voltages, dwell, ramp and current cutoffs will be explored.

The paper will further extrapolate to educate OEMs the full guidelines regarding what HiPot testing is designed for and the difference for high potential individual net testing.

Conclusions
•Hi-Pot test is for test of dielectics and core insulation
•High Voltage Test is for net to net testing
•IPC TM-650 notes two conditions for Hi-Pot, A- 500V and B-1000V
•3 options for test, Manual, Fixture and Full Automation
•Automated Verifcation
•Removes operator intervention
•Security against escapes
•Increased efficiency

Initially Published in the IPC Proceedings

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