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Reflow Optimization for MLP Components
Reflow Optimization for MLP Components
Paper covers sigma methodology for developing experiments for mounting 6x6 DrMOS Molded Lead Package components.
Production Floor

Authored By:
Dennis Lang
Fairchild Semiconductor
San Jose, CA USA
,{url:'http://www.circuitinsight.com/videos/reflow_optimization.mp4'},{url:'http://www.circuitinsight.com/videos/programs_final.mp4'}], clip:{autoBuffering:true, autoPlay:true, scaling:'scale' } }).ipad();
Transcript
The widely publicized and studied implementation of lead free solders has led to increased scrutiny on the solder joint formation for surface mount technology electronic components.

During the lead free transition, packaging technology for power semiconductor components increasingly embraced molded leaded package technology.

Due to the application demands of power devices, namely temperature control and reliability, many end users have placed considerable emphasis on process void minimization.

Experiments have shown that increasing the quantity of solder paste printed will often minimize process voiding, but incidences of solder balling and beading often increase.

Due to their comparative complexity, multi-die molded leaded packages have shown to be more sensitive to solder process design and control.

This created the need for a thorough investigation of solder process parameters, and a method to collect and analyze the data from a set of experiments to optimize the process.

No previous process found by the experimenters was found to meet the needs of the problem.

This paper demonstrates a six sigma based methodology for developing a rigorous design of experiments for determining the best process for surface mounting molded leaded package components.
Summary
The widely publicized and studied implementation of lead free solders has led to increased scrutiny on the solder joint formation for surface mount technology electronic components. During the lead free transition packaging technology for power semiconductor components increasingly embraced molded leaded package (MLP) technology. Due to the application demands of power devices, namely temperature control and reliability, many end users have placed considerable emphasis on process void minimization.

Experiments have shown that increasing the quantity of solder paste printed will often minimize process voiding, but incidences of solder balling and beading often increase. Due to their comparative complexity, multi-die MLPs have shown to be more sensitive to solder process design and control. This created the need for a thorough investigation of solder process parameters, and a method to collect and analyze the data from a set of experiments to optimize the process. No previous process found by the experimenters was found to meet the needs of the problem. Demonstrated in this paper is a six sigma based methodology for developing a rigorous design of experiments for determining the best process for surface mounting a 6x6 DrMOS MLP component.

Critical factors will be identified and treated statistically using DMAIC methods.
Conclusions
Six sigma methods and tools allowed the teams to quickly resolve a complicated problem with eighty four discrete combinations of surface mount process factors. Splitting solder paste prints, varying areas, varying outside pin coverage, and changing the reflow profile were all tried and the effects analyzed. The differences studied were sometimes subtle, which without proper experimental methodology would have been difficult to distinguish as meaningful improvements. The tools gave team members a superior way to set up and organize DOEs, with clear DOE set ups easily communicated between engineers and technicians.

At the customer site, the statistical evidence was powerful data to persuade both the customer team members, and their management to make changes. These efforts were not in vain. This product now ships in very high volume across multiple manufacturing sites with no report ed failures attributed to the surface mount process.
Initially Published in the IPC Proceedings
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