Electronics Assembly Knowledge, Vision & Wisdom
Relationship Between Via Size and Cleanliness
Relationship Between Via Size and Cleanliness
This paper explores multiple via sizes, cleaning, and what may be the most viable option for producing good performing product.
Production Floor

Authored By:
Eric Camden
Foresite, Inc., Kokomo, IN USA
,{url:'http://www.circuitinsight.com/videos/via_size_clean.mp4'},{url:'http://www.circuitinsight.com/videos/programs_final.mp4'}], clip:{autoBuffering:true, autoPlay:true, scaling:'scale' } }).ipad();
Transcript

Micro-via technology has many advantages: it requires a smaller designed area, which saves the board size and weight, using less space, allowing for a smaller PCB, which can results in lower costs, and the micro-via allows for better performance due to a shorter pathway.

The practical definition of micro-via technology is "high density printed circuit substrates that employ via diameters of under 10 mils, or 250 microns, in diameter."

With all the benefits of the micro-via, cleaning issues are often overlooked. Bare board manufacturers have been effective in cleaning the larger vias; however, is the cleaning process as effective on the smaller vias?

Failure analysis data suggests that etch residues from the build process are being left in the micro-vias causing corrosion and electromigration failures. If residues are in vias under components, the risk of contamination related failures increases.

Ion chromatography results repeatedly reveal the importance of board and component cleanliness as an indicator of product performance. Manufacturers have historically used a standard rinse process with heated de-ionized water after etch to remove process residues.

This process has been effective with traditional larger vias, but may no longer be an effective process with micro-via technology. This paper will explore multiple via sizes, different approaches to cleaning, and what data shows may be the most viable option for producing good performing product.

Summary
Microvia technology has many advantages: it requires a smaller designed area, which saves the board size and weight, using less space, allowing for a smaller PCB, which can results in lower costs, and the microvia allows for better performance due to a shorter pathway. The practical definition of microvia technology is "high density printed circuit substrates that employ via diameters of under 10 mils [250 microns] in diameter."

With all the benefits of the microvia, cleaning issues are often overlooked. Bare board manufacturers have been effective in cleaning the larger vias; however, is the cleaning process as effective on the smaller vias? Failure analysis data suggests that etch residues from the build process are being left in the microvias causing corrosion and electromigration failures. If residues are in vias under components, the risk of contamination related failures increases.

Ion chromatography results repeatedly reveal the importance of board and component cleanliness as an indicator of product performance. Manufacturers have historically used a standard rinse process with heated de-ionized water after etch to remove process residues. This process has been effective with traditional larger vias, but may no longer be an effective process with microvia technology. This paper will explore multiple via sizes, different approaches to cleaning, and what data shows may be the most viable option for producing good performing product.
Conclusions
Like every assembly process many cleanliness parameters should be taken into consideration when looking at acceptability criteria for your specific product. There are other unknowns that could also play a significant part in the addition of residues, these include but are not limited to, cleaning parameters at each different board supplier for bath life change out indicators, temperature of rinsing, quality of incoming rinse water, belt speed, impingement angles, pressure of rinse etc.

If you plan on using microvias in your design and especially if any of these are to be open and placed under a low stand-off component you need to be very aware of the cleanliness level you are starting with to avoid issues after product is introduced into the field relating to contamination.

A localized extraction of various via sizes on your prototype boards and ion chromatography of solution can give you the information you need to determine if your supplier is effectively rinsing off all process residues and lowering the risk of failures. At that point the decision can be made to either rewash the boards with some sort of saponifier and retested to assess via cleanliness.

Common sense would tell us that if there are issues with microvia contamination the answer may be to plug them and assume that the residues won‟t leach/outgas onto the surface of the assembly but at the same time it needs to be noted that if contamination levels, even in plugged vias, are high enough corrosion can still occur within the via.
Initially Published in the IPC Proceedings
Submit A Comment

Comments are reviewed prior to posting. Please avoid discussion of pricing or recommendations for specific products. You must include your full name to have your comments posted. We will not post your email address.

Your Name


Company


E-mail


Country


Comments


Authentication

Please type the number displayed into the box. If you receive an error, you may need to refresh the page and resubmit the information.



Related Programs
bullet pH neutral Cleaning Agents - Market Expectation & Field Performance
bullet White Discoloration After Ultrasonic Cleaning
bullet Defluxing for New Assembly Requirements
bullet Cost Comparison: Batch and Inline Cleaners
bullet Mixed Cleaning for Tin-lead and Lead-free
bullet Is No-Clean the Trend for QFN Components?
bullet How Clean is Clean?
bullet Pros and Cons of Cleaning No-clean
bullet Mixed Cleaning - No Clean and Water Soluble
bullet Cleaning PCBs - Understanding Todays Needs
More Related Programs
About | Advertising | Contact | Directory | Directory Search | Directory Submit | Privacy | Programs | Program Search | Sponsorship | Subscribe | Terms

Circuit Insight
6 Liberty Square #2040, Boston MA 02109 USA

Jeff Ferry, Publisher | Ken Cavallaro, Editor/Business Manager

Copyright © Circuitnet LLC. All rights reserved.
A Circuitnet Media Publication