Electronics Assembly Knowledge, Vision & Wisdom
Design for Testability to Overcome Functional Board Test Complexities
Design for Testability to Overcome Functional Board Test Complexities
In this paper the author reviews how Design for Testability techniques can be an effective way to reduce functional board test programming complexity.
Production Floor

Authored By:
Louis Y. Ungar
Advanced Test Engineering (A.T.E.) Solutions, Inc.
,{url:'http://www.circuitinsight.com/videos/programs_final.mp4'}], clip:{autoBuffering:true, autoPlay:true, scaling:'scale' } }).ipad();
Summary
Manufacturers test to ensure that the product is built correctly. Shorts, opens, wrong or incorrectly inserted components, even catastrophically faulty components need to be flagged, found and repaired. When all such faults are removed, however, functional faults may still exist at normal operating speed, or even at lower speeds. Functional board test (FBT) is still required, a process that still relies on test engineers' understanding of circuit functionality and manually developed test procedures.

While functional automatic test equipment (ATE) has been reduced considerably in price, FBT test costs have not been arrested. In fact, FBT is a huge undertaking that can take several weeks or months of test engineering development, unacceptably stretching time to market. The alternative, of selling products that have not undergone comprehensive FBT is equally, if not more, intolerable.

Design for Testability (DFT) techniques are effective ways to reduce FBT test programming complexity. This is accomplished by improving Observability and Controllability attributes. This often implies adding test points, but access improvements can be gained from many design activities. These include JTAG/IEEE-1149.1 boundary scan access wherever they happen to be present.

We examine some failure modes and show that many of them need to be tested with FBT. Still others require DFT to enable FBT to detect them. We suggest a more pro-active approach that purposely places boundary scan access to internal circuit locations necessary or instrumental for better tests. This approach requires test and design collaboration during the design process. Designers must understand the test requirements early enough to add the necessary access points so that path sensitization and diagnostic attributes are also improved.

When complex measurements are needed to ensure functionality, increased cost of both test equipment price and lack of availability may be limiting factors. Designs can usually accommodate existing ATEs and test set ups, provided this is done during the design process. We propose a parallel design and test engineering activity. We argue that while the potential benefits are great, the added costs are insignificantly small.
Conclusions
Manufacturing test strategies are complicated by the notion of FBT. While AOI-AXI-ICT find visible and catastrophic faults, FBT is needed to find the more obscure, subtle and often intermittent faults that can disturb circuit boards. While the clear majority, in fact 90%, of all failures are detectable without FBT we have made a compelling case why this stage of test should not be skipped.

The cost of escapes is much higher than the cost of the product or that of test and the penalty of releasing only a few bad units can be devastating. Consider the case of Samsung's Note 7 smart phone where only about 170 of the 2.5 million phones manufactured, only about 68 ppm, exploded or bust into flames. Yet it resulted in having the product recalled and discontinued at a cost in the billions of dollars. Would FBT and DFT had mitigated this. Perhaps not, but at least it strongly suggests that failure modes should not be ignored.

In this paper, we focused on failure modes. As studies by the Nuclear Energy Agency shows, many failure modes occur in the field that are difficult or impossible to detect without FBT. If FBT is not performed at manufacturing test, they may well wind up failing in our nuclear reactors. We then presented our own set of failure modes. While not all failure modes were included, Table 2 demonstrates a need to have FBT detection for many failure modes. It also demonstrates that some can only be detected if the design is testable.

We ended with a discussion on how DFT should be managed. Having design and test engineers working as a team offers many benefits and we believe it can reduce the cost of the DFT activity. Though we make a convincing case for this team effort, many organizations see this as contrary to traditions and are not eager to adopt it any time soon. We need a cultural change.

Rather than view electronics as a collection of the $10 or $15 worth of parts, we need to view it as the potential cause of a tragedy that could come in many forms and at costs far outweighing their original purchase price. It makes no sense to spend $8 to test a $15 product, but it does not have to cost that much. With DFT, test costs can be lowered while comprehensiveness is increased. As IC manufacturers have done for years, circuit board manufacturers must also invest in better test through DFT.
Initially Published in the IPC Proceedings
Submit A Comment

Comments are reviewed prior to posting. Please avoid discussion of pricing or recommendations for specific products. You must include your full name to have your comments posted. We will not post your email address.

Your Name


Company


E-mail


Country


Comments


Authentication

Please type the number displayed into the box. If you attempt to submit information and receive an error, you may need to refresh the page and insert the information again.



Related Programs
bullet Early Design Review of Boundary Scan To Enhancing Testability
bullet Combination of AOI and AVI Machines
bullet Explanation of PoP Inspection Techniques
bullet Thermal Mechanical Fatigue of a 56 I/O Quad-Flat No Lead Package
bullet Numerical Study on New Pin Pull Test for Pad Cratering
bullet Test Probe Problems After Pin-In-Paste
bullet Pb-Free Thermal Cycle Acceleration Factors
bullet Drop Test Performance of BGA Assemblies
bullet Expanding IEEE Std 1149.1 Boundary-Scan Architecture
bullet Analysis of Voiding Under QFN Packages
More Related Programs
About | Advertising | Contact | Directory | Directory Search | Directory Submit | Privacy | Programs | Program Search | Sponsorship | Subscribe | Terms

Circuit Insight
6 Liberty Square #2040, Boston MA 02109 USA

Jeff Ferry, Publisher | Ken Cavallaro, Editor/Business Manager

Copyright © Circuitnet LLC. All rights reserved.
A Circuitnet Media Publication