Electronics Assembly Knowledge, Vision & Wisdom
Evaluation of POP Assembly Under Load
Evaluation of POP Assembly Under Load
Study evaluates one pass and two pass techniques for assembly of POP devices under torsion loading to compare impact on the fatigue durability.
Production Floor

Authored By:
Vikram Srinivas, Michael Osterman
Center for Advance Life Cycle Engineering
Department of Mechanical Engineering, University of Maryland USA

Robert Farrell
Benchmark Electronics, Inc., Nashua, NH USA
,{url:'http://www.circuitinsight.com/videos/programs_final.mp4'}], clip:{autoBuffering:true, autoPlay:true, scaling:'scale' } }).ipad();
Summary
Package on Packages (PoP) find use in applications that require high performance with increased memory density. One of the greatest benefits of PoP technology is the elimination of the expensive and challenging task of routing high-speed memory lines from under the processor chip out to memory chip in
separate packages. Instead, the memory sits on top of the processor and the connections are automatically made during assembly. For this reason PoP technology has gained wide acceptance in cell phones and other mobile applications. PoP technology can be assembled using one-pass and two-pass assembly processes. In the one-pass technique the processor is first mounted to the board, the memory is mounted to the processor and the finished board is then run through the reflow oven in a single pass. The two-pass technique has an intermediate step in which the memory is first mounted onto the processor. Then, these two parts are placed in a carrier tray and reflowed. These joined devices are then mounted on the circuit board and the finished board is reflowed a second time.

The two-pass technique has a distinct advantage in that the PoPs can be checked for defects before final assembly using a non-destructive test (such as X-Ray) and hence one would expect higher yield. For this study, identical test vehicles were assembled with eight PoP packages assembled with SAC105 and SAC125 solder for the bottom BGA and top BGA respectively. One-pass technique and two-pass technique were used to assemble two test vehicles each. These test vehicles were evaluated under mechanical torsion loading to establish if method of assembly used has any impact on the mechanical fatigue durability. This was followed by failure analysis to determine failure sites. Time to failure data was plotted as Weibull 2-parameter distributions and ANOVA analysis was performed. No statistically significant difference was found in the reliability of the packages assembled using the two different techniques
Conclusions
Mechanical torsion loading was used to compare the different assembly techniques for package on package technology and no statistically significant difference was observed. The bottom nets were always found to fail first in PoP assemblies. No statistically significant difference in durability was observed for PoP technology with increased Ag content in the solder interconnects of bottom package under mechanical torsion. No difference in trend of failure distribution was observed between solder types or assembly techniques for package on packages. Pad cratering was identified to be a potential reliability concern. Use of under fill is recommended to redistribute stress uniformly and avoid trace failures.
Initially Published in the IPC Proceedings
Submit A Comment

Comments are reviewed prior to posting. Please avoid discussion of pricing or recommendations for specific products. You must include your full name to have your comments posted. We will not post your email address.

Your Name


Company


E-mail


Country


Comments


Authentication

Please type the number displayed into the box. If you receive an error, you may need to refresh the page and resubmit the information.



Related Programs
bullet Evaluation of POP Assembly Under Load
bullet Challenges of Package on Package Devices
bullet Cost Effective 3D Glass Microfabrication
bullet Embedded Packaging Technologies
bullet Fluxless Die Attach by Activated Forming Gas
bullet Panel Level Packaging
bullet Design for Flip-Chip and Chip-Size Technology
bullet Solder Bumping for Flip Chip Technology
bullet Embedded Fibers Enhance Nano-Scale Interconnections
bullet Low-Cost & High Performance Silicon Interposers
More Related Programs
About | Advertising | Contact | Directory | Directory Search | Directory Submit | Privacy | Programs | Program Search | Sponsorship | Subscribe | Terms

Circuit Insight
6 Liberty Square #2040, Boston MA 02109 USA

Jeff Ferry, Publisher | Ken Cavallaro, Editor/Business Manager

Copyright © Circuitnet LLC. All rights reserved.
A Circuitnet Media Publication