Transcript
Microchip density has at least doubled every 2 years for over 50 years as predicted by Moore’s Law. Today’s most advanced chips house nearly 50 billion transistors within a space no larger than your thumbnail. The task of cramming even more transistors into that confined area has become more and more difficult. In a new study published in the journal Nature, Penn State researchers identify a potentially game-changing remedy: seamlessly implementing 3D integration with 2D materials.
In the semiconductor world, 3D integration means vertically stacking multiple layers of semiconductor devices. This approach not only facilitates the packing of more silicon-based transistors onto a computer chip, but also permits the use of transistors made from various 2D materials to incorporate diverse functionalities within various layers of the stack, a concept known as “More than Moore.” With the work outlined in the study, the team demonstrates feasible paths beyond scaling current tech to achieve both more density as well as “More than Moore” benefits through monolithic 3D integration.
Monolithic 3D integration is a fabrication process wherein researchers directly make the devices on the one below, as compared to the traditional process of stacking independently fabricated layers. As the study shows, “Monolithic 3D integration offers the highest density of vertical connections as it does not rely on bonding two pre-patterned chips. This eliminates micro-bumps where the two chips are bonded together, so you have more space to make connections.” However, monolithic 3D integration faces significant challenges since conventional silicon components would melt under the processing temperatures.
As the researchers observe, “One challenge is the process temperature ceiling of 450 degrees Celsius for back-end integration of silicon-based chips; our monolithic 3D integration approach drops that temperate significantly to less than 200 C.” And unlike silicon chips, 2D materials can withstand temperatures needed for the process. The researchers used existing techniques to demonstrate their approach, and they are the first to successfully achieve monolithic 3D integration at this scale using 2D transistors made with 2D semiconductors called transition metal dichalcogenides.
The ability to vertically stack the devices in 3D integration also enabled more energy-efficient computing because it solved a surprising distance problem for such tiny things as transistors on a computer chip. According to the researchers, “By stacking devices vertically on top of each other, you’re decreasing the distance between devices, and therefore, you’re decreasing the lag and also the power consumption.” By decreasing the distance between devices, the researchers achieved greater density.
By incorporating transistors made with 2D materials, the researchers also met the “More than Moore” criterion. The 2D materials are known for their unique electronic and optical properties, including sensitivity to light, which makes these materials ideal as sensors. This is useful, the researchers said, as the number of “edge devices” continue to increase. Using 2D devices for 3D integration has several other advantages, the researchers said.
One is superior carrier mobility, which refers to how an electrical charge is carried in semiconductor materials. Another is being ultra-thin, enabling the researchers to fit more transistors on each tier of the 3D integration and enable more computing power. While most academic research involves small scale prototypes, this study demonstrated 3D integration at a massive scale, characterizing tens of thousands of devices.
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