Reza Ghaffarian, Ph.D.
Jet Propulsion Laboratory
California Institute of Technology Pasadena, CA USA
Numerous 3D stack packaging technologies have been implemented by industry for use in microelectronics memory applications. This paper presents a reliability evaluation of a particular package-on-package (PoP) that offers a reduction in overall PCB board area requirements while allowing for increases in functionality. It utilizes standard, readily available device packaging methods in which high-density packaging is achieved by: (1) using standard "packaged" memory devices, (2) using standard 3-dimensional (3-D) interconnect assembly. The stacking approach provides a high level of functional integration in a well-established and already functionally tested packages. The stack packages are built from TSOPs packages with 48 leads, stacked either 2-high or 4-high, and integrated into a single dual-flat-no-lead (DFN) package.
To determine thermal cycle reliability, daisy-chain packages were soldered either using lead-free or tin-lead solder with added additional daisy-chain patterns on the PCB to enable resistance monitoring of the stack at thermal cycling intervals. The 3-D stacks were bonded to the board for improving resistance to mechanical loading such as drop and vibration. A number of 2-high and 4-high 3-D stack assemblies were subjected to thermal cycling in the range of -55 degrees to 125 degrees C. The daisy-chain resistances were measured at RT and at 50 cycle intervals during thermal cycling. Test results to 500 thermal cycles are presented as well as images gathered from X-ray and optical microscopy to illustrate damage progression and to establish failure mechanisms. Furthermore, comparison was also made between 2D X-ray and X-ray tomography with optical microscopy to determine effectiveness of these non-destructive evaluation techniques. The paper concludes with a summary and recommendations for the next step of investigation.
This paper presented thermal cycle reliability evaluations of 2-high and 4-high 3D stacks built with a mix of TSOP and DFN daisy-chain package assembly. Although this particular PoP packaging technology offers advantages in 3D high-density packaging with readily available (TSOP to DFN) technology, it was found that this packaging technology does not meet minimum reliability expectations when evaluated under standard temperature cycling methods typically used in electronics packaging qualification tests for high-reliability and even most commercial applications. Characterization was performed by daisy-chain resistance evaluation followed by visual and 2D/3D X-ray inspections. Visual inspection clearly showed various levels of failures after 500 thermal cycles (-55 degrees to 125 degrees C). X-rays showed lead shifts and lead covered by adhesive that is not possible to visually inspect, though separation was observed by visual inspection.
A more robust 3D stack memory package is being offered by another manufacturer. Even though this technology uses a stack of tested TSOP memory, it uses more flexible L shaped leads extruded under the part for a more robust assembly reliability. A configuration of this package style is being evaluated with and without edge adhesive bonding. Reliability test data for this style of 3D stack packages is being gathered and to be the subject of a future paper.
Initially Published in the IPC Proceedings