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Calculating Failure Rate During Rework



Calculating Failure Rate During Rework
Is there a way to estimate the potential failure rate introduced by hand rework on one SMT part? Phil Zarrow and Jim Hall, The Assembly Brothers, share their own insights to answer this question.
Board Talk
Board Talk is presented by Phil Zarrow and Jim Hall of ITM Consulting.
Process Troubleshooting, Failure Analysis, Process Audits, Process Set-up
CEM Selection/Qualification, SMT Training/Seminars, Legal Disputes
Phil Zarrow
Phil Zarrow
With over 35 years experience in PCB assembly, Phil is one of the leading experts in SMT process failure analysis. He has vast experience in SMT equipment, materials and processes.
Jim Hall
Jim Hall
A Lean Six-Sigma Master Blackbelt, Jim has a wealth of knowledge in soldering, thermal technology, equipment and process basics. He is a pioneer in the science of reflow.

Transcript


Phil
Welcome to Board Talk with Jim Hall and Phil Zarrow of ITM Consulting, the Assembly Brothers pick and place. Today we are coming to you from the ITM Consulting failure analysis cave. I do believe we have a reliability question, don't we Jim.

Jim
That is true my brother of infinite wisdom. This comes from A.F.

Is there a way to estimate the potential failure rate introduced by hand rework on one SMT part? The process involves desoldering and soldering a new part using solder iron tweezers. We are trying to understand the benefit of rework versus the potential defects induced.

Very good question. A.F., you are asking the right questions.

In my opinion, the answer is any rework potentially reduces the ultimate reliability of the assembly. Quantifying that, estimating the failure rate, or reduced reliability would be very difficult in my opinion.

The potential of overheating something, damaging some material, damaging adjacent components, creating too thick an intermetallic and so forth all are real possibilities, real risks. Estimating them is very difficult to put a number on, in my opinion.

What do you think?

Phil
I agree. And of course, one of the other things is probably to a certain degree the nature of the component itself.

Something like a passive. Just looking at the integrity of the component electrically is probably going to be a lot less vulnerable than some IC.

In fact, the IC manufacturer might have a recommendation. Most likely not, because they don't pay much attention to the process.

But some of the better ones might. Beyond that, it is a very good question to be thinking that way.

I would think that perhaps people like DFR Solutions might have done some homework on that type of thing. They might have some ideas or guidelines.

But I think it is what you said, it is going to be germane to the nature of the component.

Jim
Phil, I am looking at the last specific question. We are trying to understand the benefit of the rework versus potential defects induced.

If it is not implied, do not rework or touch up a joint unless you are sure there is a defect. You will probably create more of a problem.

This has been very common in traditional wave soldering. They touch up everything to make shiny joints.

It is generally agreed you are probably doing more damage than you are doing any good. If the joint looks good by IPC 610 standards, even if it is a little on the low side as long as it falls within those criteria, it is better not to touch it.

Phil
Absolutely. One of the ITM deadly sins of SMT is touching up for cosmetic reasons.

That is one of the biggest no-nos. What you want to do is if it a dull joint rather than just touching it up with a solder iron and make it nice and shiny, what is the root cause?

Why is it dull? Is your cleaning sufficient coming out of reflow or whatever process your soldering, that is one thing?

And the other thing is actually discerning what is a symptom? What is a defect?

And of course, one of the favorite areas of that is voids. If you start to see a certain degree of voids with the BGA balls you automatically say oh it's over the limit we better rework it.

And risk reworking a BGA, not only the costs but the risks. Where are those voids located?

Near the interfacing surfaces? What is the quantification?

How does that comply with the IPC recommendations and things like that. That is one of the eternal questions on voids anyway - defect or symptom?

And you've got to really analyze it. Avoid doing things for cosmetic reasons, as my brother has said.

Thank you for listening to Board Talk.

Whether you are touching up or doing your primary soldering whatever you do, please don't solder like my brother.

Jim
Don't solder like my brother.

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