Research
Leadless Flip Chip PLGA for Networking Applications
Influence of Manufacturing Quality on Thermomechanical Stress of Microvias
Designing a High Performance Electroless Nickel and Immersion Gold
Innovative of CU Electroplating Process for Any Layer Via Fillwith Planer Via Top and Thin Surface Copper
Acoustic Micro Imaging Analysis for 3D Packages
Conformal Coatings in Preventing Resistor Silver Sulfide Corrosion
Rework Challenges for Leading Edge Components BGA, QFN and LED
Compatibility and Aging for Flux and Cleaner Combinations
MORE RESEARCH
Latest Industry News
Foxconn installs advanced packaging equipment at China plant
Foxconn installs advanced packaging equipment at China plant
Here’s the latest proof that Apple is fixing the iPhone notch
The iPhone 12’s strong momentum helps Apple to another huge quarter
Electronics Industry Faces Supply Disruptions
Foxconn's Zhengzhou plants on hiring spree
Apple demolishes earnings expectations, but stock falls after iPhone chip supply warning
How an AI-Applied Supply Chain Enables Efficiency
MORE INDUSTRY NEWS

New Approaches to Develop a Scalable 3D IC Assembly Method



New Approaches to Develop a Scalable 3D IC Assembly Method
In this paper, we will discuss various assembly options and the challenges posed by each.
Production Floor

DOWNLOAD

Authored By:


Charles G. Woychik Ph.D., Sangil Lee, Ph.D., Scott McGrath, Eric Tosaya and Sitaram Arkalgud Ph.D.
Invensas Corporation
San Jose, CA

Summary


The challenge for 3D IC assembly is how to manage warpage and thin wafer handling in order to achieve a high assembly yield and to ensure that the final structure can pass the specified reliability requirements. Our test vehicles have micro-bumped die having pitches ranging from 60um down to 30um. The high density of pads and the large die size, make it extremely challenging to ensure that all of the micro-bump interconnects are attached to a thin Si-interposer. In addition, the low standoff between the die and interposer make it difficult to underfill.

A likely approach is to first attach the die to the interposer and then the die/interposer sub-assembly to the substrate. In this scenario, the die/interposer sub-assembly is comparable to a monolithic silicon die that can be flip chip attached to the substrate. In this paper, we will discuss various assembly options and the challenges posed by each. In this investigation, we will propose the best method to do 2.5D assembly in an OSAT(Outsourced Assembly and Test) facility.

Conclusions


The semiconductor fabs can produce robust and reliable devices with TSVs.

A PF3 type of process, is compatible with an OSAT facility, and can produce 3D IC packages that can meet the challenges of JEDEC reliability specifications.

This work has shown that a high yielding MBD to Si-ITP process is achievable.

The manufacturing infrastructure exists to assembly in high volume these types of packages using existing OSAT manufacturing infrastructure.

Initially Published in the IPC Proceedings

Comments

No comments have been submitted to date.

Submit A Comment


Comments are reviewed prior to posting. You must include your full name to have your comments posted. We will not post your email address.

Your Name


Your Company
Your E-mail


Your Country
Your Comments



Board Talk
What Causes Solder Icicles During Wave Soldering
Modify Rework Procedures for Assemblies Fabricated Using OSP?
Can High Particle Concentrations Impact PCB Assembly?
Review of Tin-Copper and Tin-Nickel Intermetallic Thickness
Moisture Barrier Bag Issues
Trouble With Skewed DPAK Components
Can Mixing Wave Solder Pallets Cause Contamination?
How to Reduce Voiding on QFN Components
MORE BOARD TALK
Ask the Experts
Suggested Limit for PCBA Heat Cycles
Average Temperature/Humidity for an Electronics Assembly Facility?
ENIG Solderability Issues
Very Low Temp PCBs
0201 Pick & Place Nozzle Plugging
IPC-A-610 Class 3 - IPC-A-600 Class 2
BGA Solder Ball Collapse
Baking After Cleaning Hand Placed Parts
MORE ASK THE EXPERTS