Authored By:
Maarten Cauwe, imec-Cmst, Zwijnaarde, Belgium
Bart Vandevelde, imec, Leuven, Belgium
Chinmay Nawghane, imec, Leuven, Belgium
Marnix Van De Slyeke, ACB, Dendermonde, Belgium
Erwin Bosman, ACB, Dendermonde, Belgium
Joachim Verhegge, ACB, Dendermonde, Belgium
Alexia Coulon, Thales Alenia Space, Charleroi, Belgium
Stan Heltzel, European Space Agency, ESTEC, Noordwijk, The Netherlands
Summary
High density interconnect (HDI) printed circuit boards (PCBs) and associated assemblies are essential to allow space projects to benefit from the ever increasing complexity and functionality of modern integrated circuits such as field programmable gate arrays (FPGAs), digital signal processors (DSPs) and application processors. Increasing demands for functionality translate into higher signal speeds combined with an increasing number of I/Os. To limit the overall package size, the contact pad pitch of the components is reduced. The combination of a high number of I/Os with a reduced pitch places additional demands onto the PCB, requiring the use of laser drilled microvias, high aspect ratio core vias and small track width and spacing. While the associated advanced manufacturing processes have been widely used in commercial, automotive, medical and military applications; reconciling these advancements in capability with the reliability requirements for space remains a challenge.
This paper provides an overview of the ongoing ESA project on high-density PCB assemblies, led by imec with the aid of ACB and Thales Alenia Space in Belgium. The goal of the project is to design, evaluate and qualify HDI PCBs that are capable of providing a platform for assembly and the routing of small pitch AAD for space projects. Two categories of HDI technology are considered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked microvias (complex HDI). In this paper, the qualification of the basic HDI technology in accordance with ECSS-Q-ST-70-60C is described. The results of the thermal cycling, interconnection stress testing (IST) and conductive anodic filament (CAF) testing are provided. The test vehicle design and test parameters for each test method are discussed in detail.
Conclusions
During the workshop, the relevant AADs for space applications were identified. Based on the mechanical and functional requirements of these components, the technology parameters and associated design rules were determined. Two categories of HDI technology are considered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked microvias (complex HDI).
This paper presents the main results of the qualification test flow for the basic HDI technology. The through going vias and buried vias reach the required IST endurance of 400 cycles. The microvia configuration for the 0.8 m pitch fanout might be the cause of the early failure in IST. Electrical monitoring during thermal cycling showed only a minimal increase in resistance for both temperature ranges. Microsectioning after cycling did not reveal any cracks initiating in the barrel of the buried via nor any anomalies in the microvias. For the CAF testing, no failures are observed between microvias at 0.5 mm pitch, buried vias at 1.0 mm pitch or PTHs at 1.27 mm pitch. Some failures occur between buried vias at 0.8 mm pitch. Most failures are detected in the via-to-plane test structures, especially for the PTHs. All other tests in the qualification test flow were passed successfully.
The qualification of the basic HDI technology is only the first step in this extensive study on HDI technology for space applications. An extensive reliability assessment is underway. Various test methods for microvias will be evaluated in order to arrive at a test flow that can assure an adequate confidence level for both procurement and qualification.
Initially Published in the SMTA Proceedings
|
