Authored By:
Trent Uehling, CS Foong
NXP Semiconductors
TX, USA
Summary
Coreless embedded-trace flip chip package substrate technology has emerged as an effective solution for Bond-on-Trace (BoT) chip attach in Flip-Chip Chip-Scale Package (FCCSP) technology. With this substate technology comes a reduction in package substrate thickness by 75% or more. Since the semiconductor die and package mold cap thickness do not scale at the same rate, the resulting coreless package has a higher die and mold cap thickness to substrate thickness ratio than conventional cored packages.
In this situation, the silicon die and mold compound mechanical properties become more dominant in affecting package warpage both at room temperature and during PC board assembly reflow. The differences may manifest in shape, magnitude and direction of package warpage. In Surface Mount Technology (SMT) board attach, the impact of package warpage can be most observed at the package corners. Bending of the corners towards the PC board, sometimes referred to as “frowny face” at peak reflow temperature can result in bridged solder joints, while lifting of the corners, often referred to as “smiley face” can result in Head in Pillow (HiP) defects.
In this study, PC board design and solder stencil designs are evaluated for board attach defectivity for core-less FCCSP packages. It is observed that with properly engineered package materials and mechanical configuration, as well as optimization of PC board pad design, a robust board assembly solution exists for thin FCCSP packages.
Conclusions
A robust board assembly recipe is demonstrated for thin FCCSP packages with reflow warpage values of up to 110μm or higher. Keys to a robust board assembly process are:
- Board reflow profile verified with temperature sensors located at package top and BGA solder joint.
- Component top and BGA solder joint temperatures less than 245℃ during reflow.
- Non-soldermask defined PC board pad design at a minimum in package corners.
- Solder stencil aperture diameter matching PC board pad diameter or slightly reduced.
- Stencil apertures in corner regions reduced by 10% to 15%.
Best results were achieved with NSMD board pad design in corner regions which are defined by a 3 × 3 BGA array and all other BGA pads designed with a mix of SMD on ground planes and NSMD elsewhere. This “corner NSMD” design results in higher overall gap height while still creating the “reservoirs” in the corner locations into which molten solder can flow during the dynamic movement of the package. Where SMD pads are used, it is recommended that the SMD solder resist opening is 0.050mm larger than the NSMD pad diameter used elsewhere.
The infrared or convection reflow requires a solder joint temperature (SJT) of 235 - 245°C, not exceeding 245 °C, and should follow the recommendation of the solder paste manufacturer, including the solder alloy being used. NXP recommends that Package Peak Temperature (PPT) should not exceed 245 °C, as higher temperatures may contribute to soldering defects.
Initially Published in the SMTA Proceedings
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