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Panel Level Package (PLP) – Scaling up Fan-Out Packaging
Materials Tech |
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Authored By:Burton Carpenter, Mollie Flick NXP Semiconductors TX, USA Kuan Hsiang Mao, Cliff Kuo, Vanessa Tan, Anita Chou NXP Semiconductors Kaohsiung, Taiwan Dominic Koey NXP Semiconductors Petaling Jaya, Malaysia SummaryThe persistent push for electronics miniaturization calls for a different approach to make packages smaller, higher performance and lower cost. Fan-out (FO) packages are well suited to serve this market trend. Via interconnects between the chip and package RDL (redistribution layers) provide higher interconnect density and lower inductance than traditional FC (flip chip) or WB (wire bond) connections. Furthermore, elimination of substrate or leadframe pieceparts simplifies the supply chain. FO packages are used in a range of end market applications including mobile, IOT (internet of things), consumer, industrial, automotive and AI (artificial intelligence). The initial FO package manufacturing format was identical to a 200mm wafer to leverage existing WLCSP (wafer-level chip scale package) infrastructure. This FOWLP (fan-out wafer-level package) met performance requirements, but the small round manufacturing form factor proved inefficient, especially for lager package sizes. Later expansion to 300mm slightly improved efficiency and utilization. However, the large (up to 700mm) rectangular format utilized by PLP (panel level package) is a game changer. While similar, the PLP final package is not identical to a FOWLP. Differences in materials, process, and final structure required package reliability validation. This paper summarizes reliability results for a 0.5mm pitch, 5mm PLP with one RDL layer. The package passed all component level and board level stresses for mobile and commercial applications. Margin was verified when it also passed all read points at >2x the required durations. Freestanding component package stresses were JEDEC MSL1/260°C (moisture sensitivity level 1), HAST 110°C (highly accelerated stress test), HTSL 175°C (high temp storage life). Board level reliability (BLR) included both daisy-chain and functional parts cycled from -40°C to +125°C. ConclusionsA Panel Level Package (PLP) test vehicle (TV) was designed and stressed to demonstrate reliability in mobile and commercial applications. In summary:
Initially Published in the SMTA Proceedings |
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