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Development of a High-Density Adaptive Redistribution Technology for Embedded High I/O Components
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Authored By:Lars Böttcher, Ruben Kahle, Claudia Landstorfer, Dionysios Manessis, and Andreas Ostmann Fraunhofer Institute for Reliability and Microintegration (IZM) Berlin, Germany SummaryThe industry's increasing demand for high-performance electronic devices with better functionality, lower power consumption and higher speed is driving innovation in advanced packaging technology. Improving the performance of semiconductor chips and advancing packaging features are critical. One solution to producing high performance electrical systems to perform computationally intensive functions in volume constrained products is the use of miniaturized packages with advanced embedded components. In addition to requirements such as sufficient yield from the lithography process itself, to avoid losing high density and valuable components, an important issue in RDL formation is registering each layer of the production board to the corresponding component during lithography. One solution is to measure the deviation of the target from the actual position, then digitally calculate and re-route the connections in the RDL pattern, and finally process the adapted data into raster image data to perform a maskless direct imaging process. [1], [2]. This paper presents the development of the necessary technology blocks for high-density redistribution layers, required to realize such organic substrate-based packages. The technology approach used is an advanced semi-additive processing (aSAP) at large panel level. This technology involves the use of dielectric layers, such as ABF or similar, PVD seeding and additive electrolytic copper deposition. It also describes the use of thin PVD seed layers below 100 nm, the incorporation of plasma processes to dry etch photoresists, to clean the surface and to etch back seed layers on 18”x24” / 610 mm x 457 mm panels. Results from the EU-funded CHARM project are also described. Here, in close cooperation with AT&S, large dies of 26mm x 18mm were embedded using low CTE core material and dielectric thin film, Ajinomoto Build Up Film. During the embedding process performed by AT&S, ABF material was used to symmetrically embed temporary fixed components using a carrier. After exposing the copper pillars (30 μm diameter) through the BU film, PVD metal deposition was used to seed the surface with titanium and copper. To connect the embedded components, IZM developed an adaptive patterning process consisting of an optical measurement routine and software to digitally correct the manufacturing data. The adapted data is fed into a maskless lithography tool so that each unique device on each unique panel is registered. In addition, results are presented on how the Semi-Additive Process (SAP) itself can be advanced by using an improved direct imaging process on an embedded die to achieve a resolution of 5 μm L/S despite topography and roughness effects. ConclusionsThe development of a process technology for high density organic substrates, based on advanced semi additive processing was successfully demonstrated. Different technology blocks for vertical and horizontal interconnects were established, and the advantages and disadvantages of the different via technologies were determined as a result. In addition, the RDL processing was optimized and alternative process option implemented. Within the EU project “CHARM”, a successful development of RDL processing for fine L/S structures, which is of paramount importance for fan-out embedded modules with high I/O dies inside, as well in general for HDI substrate manufacturing was achieved. The work done has firstly developed all the core steps for RDL processing, namely the adaptive imaging taking into account the die shifts and twists, rasterization of the imaging data and the final implementation of direct imaging in combination with profound semi-additive processing, reaching even copper structures at 3.5μm L/S. In turn, the developed RDL processes were successfully demonstrated on the computing module manufactured by AT&S, where on one computing panel with four large dies, very fine copper structures at 5μm L/S were achieved as required in the compute module. The R&D work on RDL processing will further build on the CHARM latest results toward even finer L/S structures at high yield for large industrial format panels. Initially Published in the SMTA Proceedings |
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