Norman J. Armendariz, PhD, Raytheon, Andover, MA
QFN- Quad Flat No-lead SMT-surface mount technology components continue to be increasingly used and also becoming smaller for applications further requiring a high level of thermal performance and reliability. QFN device thermal pad regions have been observed w/ excessive void densities >30% in area, which limits the thermal conductivity or performance of the device and often requires subsequent costly rework. Voids also become more dominant for smaller devices as the surface area of the thermal pad regions decrease, but voids may not correspondingly reduce in size or density. Using various reflow profiles, solder paste volumes and over-print values showed a statistically significant reduction of large voids and void density using the solder paste over print method. In addition, void formation and escape paths were demonstrated using x-ray imaging technology equipment that can be programmed to simulate an actual SMT surface mount technology reflow profile on a thermal platform or hot plate and provide real-time X-ray imaging recording the materials physical and void behavior.
Solder paste over-printing on QFN I/O pads reduced the void density and largest voids ~ 50% on both QFN MLF 16 and 52 thermal pads at 40 mil OP.
QFNs with THVs-through-hole vias showed significantly less voids, but solder paste “wicked” through to other side.
Solder joint bridging was observed at 30, 40 mils for QFN 52 and QFN MLF 16 at 40 mils overprinting. Not clear if the daisy-chain “looped” Cu circuitry underneath soldermask may have contributed to I/O pad solder bridging by providing a thermal path for each I/O pad solder paste print to follow towards each other.
Video images showed the process voids formed just before the I/O solder spheres melted, which melted before the thermal pad solder spheres.
Process voids formed tear drop shapes that moved and escaped towards the edge and also disappeared in thermal pad centers indicating a ceiling path escape.
Recommend solder paste over-printing for QFNs that require thermal pad void reduction, but taking into
account the limitations of QFN I/O pad edge-to-edge spacing and distance from nearby pads or components.
Initially Published in the SMTA Proceedings