Saminda Dharmarathna, Sean Fleuriel, William Bowerman, Jim Watkowski, Kesheng Feng
MacDermid Alpha Electronics Solutions, 227 Freight Street, Waterbury, CT 06702
Eric Kil, Charles Bae, Leslie Kim, Derek Hwang
MacDermid Alpha Electronics Solutions, 1B-4L, B dong 2nd floor, 725-4, Wonsi-dong, Danwon-gu, Ansan-si, Gyeonggi-Do, Korea
Driven by rapid changes and markets, the electronics industry has seen massive growth over the past few decades. The short product life cycle has pushed PCB fabrication technology to its limits. Industry leaders continuously push innovations to be more competitive in the electronics manufacturing market space. In this era of electronics miniaturization, technologies that generate high yields with lower costs, such as High-Density Interconnects (HDI), Semi-Additive Processing (SAP), and Modified Semi-Additive Processing (mSAP), are widely utilized. Most of these technologies are not new to the electronics industry, but are common processes in IC substrate and PCB fabrication. They help maximize the PCB real estate usage by allowing fabricators and designers to build up multilayer devices. Figure 1 shows examples of multilayer designs that require multiple metallization and etching steps to achieve the desired designs and thicknesses.
Etching has become a crucial aspect of PCB fabrication. With the increasing number of layers, the risk of failure grows exponentially. Hence, a great deal of attention has been paid to the Cu deposit and how it reacts to etching. Higher technologies require many etching steps, during which uneven etching, pinhole formation, pitting or V-pitting, become significant issues . These defects can cause severe reliability issues for the final product . Innovative Cu electroplating solutions are required that produce Cu deposits with higher resistance to V-Pitting. Fabricators currently resolve these issues by baking the plated panels for several hours, which increases the process cost and negatively affects production output. The focus of this study was to investigate the underlying mechanism of V-pitting and to develop a process to withstand or resist the pitting. This phenomenon is called “V-piting“ due to the characteristic shape of the pits.
The process discussed here also showed excellent via fill and through hole (TH) plating capability in the same plating bath for core layers of HDI and IC substrates in a one-step DC process. Vias were filled with <5 microns or zero dimple and no voids or defects. Mechanical properties met and exceeded the IPC class III standards thus satisfying the requirements of a highly reliable copper electroplating process (tensile strength => 49,000 psi, elongation > 25%). A bath aging study and a DOE were completed for the process. SEM, XRD, and FIB data will also be presented
An innovative DC acid copper process for simultaneously filling vias and plating through-holes is introduced in this
work. This new formulation shows excellent V-pit resistance during subsequent flash etching processes. A wide variety of via geometries can be filled with minimal dimple while maintaining excellent through hole plating performance. A DOE was conducted to further optimize the performance. Through varying the leveler and brightener concentrations, the DOE identified these two components as major contributors to the desired deposit properties. The tensile strength and elongation of these Cu deposits remained consistent as the bath aged and passed IPC Class III. All the additive components utilized in these processes can be analyzed with common analytical tools used in the industry.