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Creating Reusable Manufacturing Tests for High-Speed I/O

This paper illustrates high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and a strategy for testing them with SIs within FPGAs.
Analysis Lab


Authored By:

Louis Y. Ungar, Neil G. Jacobson, T.M. Mak,
A.T.E. Solutions, Inc.
El Segundo and San Jose, CA


There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second(Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically.

Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA.

By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol.

Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.


Since an ATE is permanently configured at the time it was designed, it is not flexible to keep up with UUT technology improvements. Test instruments may be updated more frequently, but they are also years behind UUT technology advancements. Using FPGA-based Sis instead of, or in addition to the ATE test instrument, is a novel concept because FPGA technology is much closer in specifications to UUTs we are likely to encounter in today’s production.

It is especially appropriate for high-speed I/O test applications. Traditional instrumentation technology suffers from the need to be general-purpose so that more buyers can absorb the cost of development. For a functional ATE to be able to test today’s high-speed I/O it needs to be flexible and dynamic, so it can readily change with the need for ever-increasing speed and complexity. Because this is a monumental requirement, we have seen most ATE suppliers shy away from the functional board test (FBT) market. Instead, test engineers are tasked not only with test program development but also with designing and integrating the collection of instruments they need to create their own ATE. This often cuts into their test development times and often require lead times that can impact time-to-market.

In this paper, we propose that the SI in an FPGA is a better solution. Not only does it improve access to the UUT by being physically closer and reducing impedance and noise, but we believe this approach reduces test engineering effort both in the short term and in years to come. In the short term, it offers test engineers more capable instrumentation than those available from general-purpose designs. While complex SIs need to be designed, we believe they are more cost-effective than using that same time and effort in test program development. Even if this does not prove to be the case for every SI, the long-term benefits of reuse will reap a profit. As the test engineering community develops more SIs and more test sets, a library can be built that houses both SIs and tests. Test engineers will be able to search these libraries for tests and SIs they need for their applications. Whether sold or accessible from an open source, with this approach, test sets will be available that will be reusable, scalable and profitable for the most current and capable FPGAs available today and in the future.

As more test engineers use and reuse the library of tests and SIs, they will scrutinize them and thereby perform a peer review. If an error is found, that information can be fed back to the source of the reusable test from which prior and future users of that test can benefit. Others who have used those tests previously can be notified of mistakes found. Ultimately the veracity of reusable test routines will improve as newer revisions are created. The tests will become more accurate and comprehensive, resulting in better designs, manufacturing, test and greater customer satisfaction.

Initially Published in the SMTA Proceedings


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