Andrew Mawer, Tara Assi, Steve Safai and Trent Uehling
NXP Semiconductors N.V.
Austin, TX, USA
Volumetric miniaturization of semiconductors and associated packaging is one of the largest driving forces within the industry. Initially motivated by the demand for smaller, more efficient and feature rich mobile electronics, this design trend has evolved and expanded across numerous applications. One example of a device designed to minimize size and maximize performance is the package that houses what is currently believed to be the world's smallest 64 bit microprocessor [1, 2]. The processor is designed for applications such as Internet of Things (IoT) gateways, portable entertainment platforms, high performance portable storage applications featuring mobile HDD and mobile storage for rechargeable devices.
The package chosen for this processor is a molded plastic land grid array (PLGA) because the final mounted height is kept to a minimum while maintaining robustness and reliability requirements. The package itself is only 9.6 mm x 9.6 mm x 0.805 mm. This paper explores the packaging design, SMT assembly process, and board level reliability testing for this package. The results of these evaluations are discussed as well, including warpage versus reflow, board-level thermal cycling, JEDEC drop and IPC bend testing performance. All of the evaluations and testing performed to date indicates that the flip chip PLGA is a robust packaging solution that meets or exceed the requirements of its various intended applications.
During the various aspects of package and surface mount process development and associated board-level reliability testing for a novel, miniaturized 211 pin FC PLGA for high performance networking and IoT applications, the following conclusions were drawn:
1. Excellent SMT assembly yields were achieved with the combination of overprinting (1.61:1 aperture to pad ratio) solder paste on the 0.5 mm pitch perimeter LGA pads only and the addition of approximately 100 muon of preapplied solder to all the LGA package pads. The resulting joint was a compromise between traditional BGAs and LGAs.
2. The component displays <40 muon bottomside flatness both at room temperature and throughout the entire reflow which is more than 2x better performance than any current, known industry standards.
3. Board-level thermal cycling performance met the projected requirements for intended applications with first failure in -40 to 125 Celsius cycling at greater than 800 cycles with NSMD and greater than 400 cycles with SMD PCB pads. Solder joint fatigue fractures with the SMD PCB pads were predominantly at the PCB pad interface. The opposite was true for the recommended NSMD PCB pads.
4. The fact that the die shadow was completely over the coarser pitch (0.8 mm) center array of LGA joints possibly helps to explain the good thermal cycling performance.
5. The small body size along with the larger corner pads were believed to be part of the reason for the excellent performance in 1500 Gs JEDEC drop and 13,000 muon strain IPC monotonic bend with no failures recorded in either test with either SMD or NSMD PCB pads.
6. Nets for monitoring the integrity of the die to substrate interconnect were included in the daisy-chain test vehicle. Vias and traces in the substrate were also included in this net. No failures were recorded on these nets in any of the testing performed indicating a very robust connection within the component.
Initially Published in the SMTA Proceedings