Improve SMT Yields Using Root Cause Analysis in Stencil Design

Improve SMT Yields Using Root Cause Analysis in Stencil Design
Paper covers SMT challenges including practical stencil design recommendations to eliminate defects and improve yields during the printing process.
Production Floor


Authored By:

Greg Smith
FCT Assembly, Inc.


Reduction of first pass defects in the SMT assembly process minimizes cost, assembly time and improves reliability. These three areas, cost, delivery and reliability determine manufacturing yields and are key in maintaining a successful and profitable assembly process. It is commonly accepted that the solder paste printing process causes the highest percentage of yield challenges in the SMT assembly process.

As form factor continues to get smaller, the challenge to obtain 100% yield becomes more difficult. This paper will identify defects affecting SMT yields in the printing process and discuss their Root Cause. Outer layer copper weight and surface treatment will also be addressed as to their effect on printability. Experiments using leadless and emerging components will be studied and root cause analysis will be presented on the following common SMT defects:

Poor Solder Paste Release: Focus will be placed on small components Solder-balls (Mid Chip Solder Beads): Stencil design to minimize solderballs Tombstoning: Improving tombstoning with stencil design Bridging at Print: Simple guidelines to eliminate bridging Bridging at SMT Reflow: What causes bridging after reflow when it is not present after print Insufficient Solder Volume at SMT Reflow: Look at the correlation of stencil design to solder volume after reflow Voiding: Design ideas to reduce voiding through stencil design

Root causes of these challenges will be identified and practical stencil design recommendations will be made with the intent of eliminating defects and improving yields during the printing process.


Identifying specific "universal" defects in the print process is critical in the effort to improve first pass yields, minimize cost, minimize assembly time and in turn to improve reliability. These "universal" defects including poor solder paste release, solder balls, tombstoning, bridging at print, bridging after reflow, insufficient solder after reflow and voiding on bottom terminated devices can all be addressed with stencil design. In many cases these defects can be greatly reduced by addressing the root cause of the specific issues.

When addressing insufficient paste at print, it has been determined it is critical to identify minimum transfer efficiencies required for acceptable solder joints and then determine minimum area ratios necessary on stencil apertures to achieve those transfer efficiencies. Solder ball issues can best be overcome using a "U-Shape" or "Inverted Homeplate" aperture and tombstoning can be improved using a "Reverse U-Shape" aperture.

The "Half Pitch Rule" is a valid and widely accepted method for eliminating bridging at print and when bridging is occurring after reflow on gull wing devices such as QFPs, it is critical to compare the size of the PWB land pad to the size of the foot of the actual component lead. Finally, voiding on ground pads of BTCs are critical and there is much work left to do to identify the best stencil design to minimize voiding percentages on these types of devices. Currently, however, the standard window pane and five dot pattern remain accepted designs.

Initially Published in the IPC Proceedings


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