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Three Dimensional Integration Focusing on Device Embedded Substrate



Three Dimensional Integration Focusing on Device Embedded Substrate
In this paper, EDA tools, TEG chips, and several evaluation equipment developed in Fukuoka are explained.
Materials Tech

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Authored By:


Hajime Tomokage
Department of Electronics Engineering and Computer Science
Fukuoka University, Fukuoka, Japan

Summary


The national research project on 3D integration technology had been carried on in Fukuoka, Japan from 2002 to 2012. The system-in-a-package (SiP) design tools STEERSIP and STEERMEMS, test element group (TEG) chips for evaluating the assembling process, and the evaluation equipment such as scanning electron and laser beams induced current (SELBIC) measurement system have been developed. In 2011, a new research center for 3D semiconductors was constructed, where the main research is on device embedded substrate and silicon interposer with through silicon via (TSV).

According to the Japan Electronics Packaging and Circuits Association (JPCA) standard on device embedded substrate EB01 and EB02, the evaluation kits for device embedded substrate are developed in order for device companies to perform function test of embedded devices with the common substrate structure.

Initially Published in the SMTA Proceedings

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