Stacking Multiple Surfaces of Transistors and Semiconducting Elements



Stacking Multiple Surfaces of Transistors and Semiconducting Elements
Chip manufacturers are looking to build up rather than out. The industry is aiming to stack multiple surfaces of transistors and semiconducting elements.
Technology Briefing

Transcript


The electronics industry is approaching a limit to the number of transistors that can be packed onto the surface of a computer chip. So, chip manufacturers are looking to build up rather than out. Instead of squeezing ever-smaller transistors onto a single surface, the industry is aiming to stack multiple surfaces of transistors and semiconducting elements — akin to turning a ranch house into a high-rise. Such multilayered chips could handle exponentially more data and carry out many more complex functions than today’s electronics. A significant hurdle, however, is the platform on which chips are built.

Today, bulky silicon wafers serve as the main scaffold on which high-quality, single-crystalline semiconducting elements are grown. Any stackable chip would have to include thick silicon “flooring” as part of each layer, slowing down any communication between functional semiconducting layers. Now, MIT engineers have found a way around this hurdle, with a multilayered chip design that doesn’t require any silicon wafer substrates and can be manufactured at temperatures low enough to preserve the underlying layer’s circuitry.

In a study appearing in the journal Nature, the team reports using the new method to fabricate a multilayered chip with alternating layers of high-quality semiconducting material grown directly on top of each other. The method enables engineers to build high-performance transistors, needed for memory and logic elements on any random crystalline surface — not just on the bulky crystal scaffold of silicon wafers. Without these thick silicon substrates, multiple semi conducting layers can be in more direct contact, leading to better and faster computation and communication between layers.

The researchers envision that the method could be used to build AI hardware, in the form of stacked chips for laptops or wearable devices. These stacked chips would be as fast and powerful as today’s supercomputers and could store huge amounts of data on par with physical data centers. This breakthrough opens up enormous potential for the semiconductor industry, allowing chips to be stacked without traditional limitations. This could lead to orders-of-magnitude improvements in computing power for applications in AI, logic, and memory.

In 2023, the research group reported that they developed a method to grow high-quality semiconducting materials on amorphous surfaces. The material that they grew was a type of 2D material known as a transition-metal dichalcogenide, or TMD, considered a promising successor to silicon for fabricating smaller, high-performance transistors. TMDs and similar 2D materials can maintain their semiconducting properties even at scales as small as a single atom, whereas silicon’s performance sharply degrades.

In their new work, the researchers sought to grow single-crystalline 2D materials at temperatures low enough to preserve any underlying circuitry. They found a surprisingly simple solution in the science and craft of metal production. When metallurgists pour molten metal into a mold, the liquid slowly “nucleates,” or forms grains that grow and merge into a regularly patterned crystal that hardens into solid form. Metallurgists have found that this nucleation occurs most readily at the edges of a mold into which liquid metal is poured.

As the researchers observe, “It’s known that nucleating at the edges requires less energy — and heat. So, we borrowed this concept from metallurgy to utilize for future AI hard ware.” The team looked to grow single-crystalline TMDs on a silicon wafer that already had been fabricated with transistor circuitry. The researchers used their new method to fabricate a multilayered chip with alternating layers of two different TMDs.

One TMD was molybdenum disulfide, a promising material candidate for fabricating n-type transistors. The other was tungsten diselenide (die-cell a-nide), a material that has potential for being made into p-type transistors. Both p- and n-type transistors are the electronic building blocks for carrying out any logic operation. The team was able to grow both materials in single-crystalline form, directly on top of each other, without requiring any intermediate silicon wafers.

A product using this technique could have 3D logic as well as 3D memory, or any combination thereof. With this growth-based mono lithic 3D method, engineers could grow tens to hundreds of logic and memory layers, right on top of each other, and they would be able to communicate very well.

Conventional 3D chips have been fabricated with silicon wafers in-between, but drilling holes through the silicon wafer limits the number of stacked layers, vertical alignment resolution, and yields. But the new growth based method addresses those issues all at once. So far, the research has demonstrated the concept with small-scale device arrays. The next step is scaling up to demonstrate professional AI chip operation.

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