As semiconductor manufactures continue deliver more capabilities in ever smaller packages, most circuit board assemblies are shrinking. High volume electronic modules are increasingly manufactured in panels of 10, 20, or even 40 identical boards. The increase in panel density is driving substantial efficiency and throughput gains on the SMT lines; however, the typical testing processes is unable to match this increased throughput.
Traditional test process throughput can easily be 5-10x slower than production throughput for these boards. This mismatch in throughput capability is forcing manufacturers to choose between high levels of untested work in process (WIP) inventory or giving up the throughput gains by slowing down the SMT line.
New technology is available to provide simultaneous electrical functional testing of all the boards in the panel, allowing test to occur in line with production. System architecture, application development, and integration will be discussed. Process benefits, including case studies, will be provided, as will industry trends that drive manufacturers to reduce human handling and scrap reworked boards. Lastly, the status of these technologies, current capabilities, limitations, and commercial rollout plans detailed.
In summary, small boards create numerous problems for electronics manufacturers because of the mismatch between production throughput and test throughput. This mismatch has been addressed by manufacturers in three ways: slowing production, batch processing with WIP Inventory buildup, and adding test capacity to match production throughput. Each of these approaches has costs and side-effects for manufacturers.
A new kind of test technology utilizes simultaneous functional testing of the entire panel of small boards. Parallel Test provides benefits to manufacturers by matching SMT line throughput. The major benefits of this new technology are: Enabling Inline Test to eliminate human handling, Provide Real-Time Data to Intelligent Digital Systems, Eliminate the need for WIP Inventory, reducing rework issues, increasing throughput and efficiency, and simplifying the process by eliminating test cell operations.
Initially Published in the SMTA Proceedings