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Status and Outlooks of Flip Chip Technology

Status and Outlooks of Flip Chip Technology
Status of flip chip technology such as wafer bumping, package substrate, flip chip assembly, and underfill is presented in this study.
Materials Tech


Authored By:

John H. Lau
ASM Pacific Technology


Status of flip chip technology such as wafer bumping, package substrate, flip chip assembly, and underfill will be presented in this study. Emphasis is placed on the latest developments of these areas in the past few years. Their future trends will also be recommended. Finally, the competition on flip chip technology will be briefly mentioned.


Wafer bumping, package substrate, assembly, and underfill for flip-chip technology have been investigated in this study. Some important results and recommendations are as follows:

Flip chip technology came from a long way. From the three-bump flip chip to 10,000-bump flip chip, and could be 50,000-bump flip chip by the year of 2020. Also, by that time, the flip-chip pitch could be as small as 30 micrometers as shown in Figure 20.

C2 bumps have better thermal and electrical performance and can go down to finer pitch (smaller spacing between pads) than C4 bumps.

The self-alignment characteristic (one of the most unique features of flip chip technology) of the C2 bumps is nowhere near the C4 bumps. Thus, mass reflow is usually applied to C4 bumped chips.

C2 bumped chips are usually assembled by TCB with high-force, while low-force is sometime used.

The advantages of TCB are for higher pin-count, finer pitch, thinner chips, higher-density, and thinner package substrates, and controlling warpage and die tilt. One of the drawbacks of TCB is throughput (compared with mass reflow).

A package substrate with ten build-up layer (5-2-5) and 10 micrometers linewidth and spacing is more than adequate to support most of the flip chips. In the past few years, because of the very high-density, high I/Os, and ultrafine pitch requirements such as the sliced FPGA, even a 12 build-up layer (6-2-6) package substrate is not enough to support the chips and a TSV interposer is needed.

As of today, TSV-interposer is very expensive. In order to lower the cost, enhance the electrical performance, and reduce the package profile, TSV-less interposers such as the Xilinx/SPIL's SLIT, Amkor's SLIM, SPIL/Xilinx's NTI, Intel's EMIB, and Cisco/eSilicon's organic interposer have been developed. This will be the trend in package substrate for high-density and performance flip chip applications.

More research and development works should be done on innovative and low-cost ETS and coreless substrates for portable, mobile, wearable, and IoTs applications. More research and development works should be done to effectively use the BOL technique to increase routing density, and thus, lower the cost and reduce the size of organic package substrate.

For the post-assembly underfill approach, the CUF or MUF is usually applied to flip-chip assemblies with mass reflow and TCB with low-bonding force methods.

For the pre-assembly underfill approach, the NUF, NCP, or NCF is usually applied before flip-chip assemblies; NUF is with mass reflow and NCP or NCF is with high-force TCB. In general, the NUF and NCP are applied on the substrate and the NCF is laminated onto the C2 bumped wafer and then diced into individual chips.

Initially Published in the IPC Proceedings


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