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2.5D and 3D Semiconductor Package Technology: Evolution and Innovation

2.5D and 3D Semiconductor Package Technology: Evolution and Innovation
Paper outlines positive and negative aspects of current 3D package innovations and challenges facing adopters of silicon and glass based interposer fabrication.
Production Floor


Authored By:

Vern Solberg
Solberg Technical Consulting
Saratoga, California USA


The electronics industry is experiencing a renaissance in semiconductor package technology. A growing number of innovative 3D package assembly methodologies have evolved to enable the electronics industry to maximize their products functionality. By integrating multiple die elements within a single package outline, product boards can be made significantly smaller than their forerunners and the shorter interconnect resulting from this effort has contributed to improving both electrical performance and functional capability.

Multiple die packaging commonly utilizes some form of substrate interposer as a base. Assembly of semiconductor die onto a substrate is essentially the same as those used for standard I/C packaging in lead frames; however, substrate based IC packaging for 3D applications can adopt a wider range of materials and there are several alternative processes that may be used in their assembly. Companies that have already implemented some form of 3D package technology have found success in both stacked die and stacked package technology but these package methodologies cannot always meet the complexities of the newer generation of large-scale multiple function processors.

A number of new semiconductor families are emerging that demand greater interconnect densities than possible with traditional organic substrate fabrication technology. Two alternative base materials have already evolved as more suitable for both current and future, very high-density package interposer applications; silicon and glass. Both materials, however, require adopting unique via formation and metallization methodologies. While the infrastructure for supplying the glass-based interposer is currently in development by a number of organizations, the silicon-based interposer supply infrastructure is already well established.

This paper outlines both positive and negative aspects of current 3D package innovations and addresses the challenges facing adopters of silicon and glass based interposer fabrication. The material presented will also reference 3D packaging standards and recognize innovative technologies from a number of industry sources, roadmaps and market forecasts.


While developers continue to explore alternative semiconductor package assembly methods to further improve yield, significant challenges remain for the newer generations of high-density and high I/O semiconductors. Although high volume consumer electronics will continue to drive similar forms of 3D package technology, high-end Telecom markets will rely on more sophisticated solutions. New generations of memory products have emerged with 30 micron pitch and two-thousand I/O and processors are entering the market that have forty-thousand I/O.

To meet the requirement for interconnecting these very large, high I/O die elements, analysts and industry roadmaps predict that companies will continue to migrate toward silicon-based or glass-based interposer technology. Although many process issues have been resolved, there are a significant number of technical issues that influence this segment of the industry. The handling and transport of the large and very thin wafers, solutions for aligning and joining very high I/O die elements, and, when the system level package is incorporated into the end product, methodologies for managing thermal dissipation.

The decision on which interposer base material is selected will be dependent on process maturity, supplier capability and cost. In order to expedite product development many are partnering with suppliers at both the frontend and backend of the semiconductor supply chain. They realize that in order to bring 2.5D and 3D package technology into the forefront they will need to develop viable and robust, high yield wafer level interposer processes.

Initially Published in the IPC Proceedings


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