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Issues With Fillets on Via Holes?

Issues With Fillets on Via Holes?
During wave solder some of the vias have concave fillets giving them a dimple effect. What can we do to create flatter fillets on via holes? Jim Hall and Phil Zarrow, The Assembly Brothers, share their own experiences and insight to answer this question.
Board Talk
Board Talk is presented by Phil Zarrow and Jim Hall of ITM Consulting.
Process Troubleshooting, Failure Analysis, Process Audits, Process Set-up
CEM Selection/Qualification, SMT Training/Seminars, Legal Disputes
Phil Zarrow
Phil Zarrow
With over 35 years experience in PCB assembly, Phil is one of the leading experts in SMT process failure analysis. He has vast experience in SMT equipment, materials and processes.
Jim Hall
Jim Hall
A Lean Six-Sigma Master Blackbelt, Jim has a wealth of knowledge in soldering, thermal technology, equipment and process basics. He is a pioneer in the science of reflow.


Welcome to Board Talk with Phil Zarrow and Jim Hall of ITM Consulting, the assembly brothers today coming to you from high atop Mount Rialto. 

We are here to talk about electronic assembly, materials, equipment, components, practices and procedures among other things and who knows where we might go with that. Jim, what is today's question?

The question is about concave via fillets causing problems. 

When we wave solder our circuit boards, some of the vias have concave fillets giving them a dimple effect. The boards function fine but we are having problems when we test using our flying probe system. 

What can we do to create flatter fillets on via holes? And this is sent in by G.F. 

The first thing is there are no flat soldered surfaces. Solder is formed by surface tension and wetting forces which are always going to give you a curved surface. Now you can try to minimize that. 

First let's make sure we agree upon what our questioner is asking. He's talking about filling via holes. These I'm assuming are plated through holes which do not have leads in them. So they go over the wave and they just fill up with solder. 

He's talking about a concave fillet on the top surface which means that the surfaces of solder in the middle of the via hole is lower than the surface of the board. That's my assumption. 

Jim I'm kind of surprised, a little puzzled as to the problem he's actually having with this flying probe in that to my knowledge flying probe generally can compensate in the Z axis for varying topography of the board and of course the test points it's going after.

So I'm not sure why it's a problem but he might want to confer with the manufacturer of the flying probe system or reexamine the programs. 

Let's address the other issue, how our friend might be able to attain somewhat flatter vias, or shall we say better filled vias.

If you think about the situation we have this concave fillet. That means we haven't completely filled the through-hole. So we're up against a classic question of how do I get better hole fill in a wave soldering process? 

In most cases we're looking for the Holy Grail which is positive top side fillets when I have a lead in the hole. Even though IPC tells us that it is not necessary even on class 3, seventy-five percent hole fill is okay. Many of us in our heart of hearts want to see that top side fillet. 

But in general getting better hole fill on plated through-holes during wave soldering is a function of optimizing the process. Adequate fluxing, proper topside preheat, proper wave parameters, depth of immersion, immersion time and so forth. 

The idea of controlling the process to get flat vias would be a really fussy process. If you increased the hole wetting you might get a convex fillet where you have a bump sticking up that might also cause problems with the flying probe. 

It's going to be really fussy to try to fine tune the wave soldering to get exactly the level hole fill in via holes across a circuit board. I see it as being probably impossible to achieve.

Check with an expert at the flying probe manufacturer. They can probably make some recommendations on compensating for the varying topography that you're dealing with. 

Beyond that we wish you the best and when you are playing around with your soldering machine and trying to make those adjustments, try not to inhale too deeply when you're over the flux pot. 

And when you hit the wave, whatever you do, please don't solder like my brother.

And don't solder like my brother.


A typical cause of false negatives in pin probe testing is the failure of the probe to penetrate flux residue, causing the probe to fail to make contact with the solder.

Since flux is normally sprayed onto the bottomside of the board, it is hard to imagine how flux residue would build up in the concave top side via fill. If the probe is programed to reach down, there should not be a problem.
Mitch Holtzer, Alpha Assembly Solutions
We get this question also and for ICT and "bed of nails applications" we have developed a "blade" type tip for the test probes. The blade keeps the tip of the probe out of the flux which often collects in the center of the via with the main contact point being the inner rim of the via with the "blades" of the probe making the contact. Blade type tips come in different angles to contact filled vias from hardly filled to flat/domed. Unfortunately with flying probe systems you are stuck with a single tip style for contacting a large variety of contact surfaces and aiming for the rim of the via instead of the center may be a possible solution. Matt Parker
Matt Parker, QA Technology Co. Inc.
Have the PCB manufacturer plug and plate the via holes or have them plug with soldermask at the bottom. I would check with the PCB house what my options are.
Sundaram, EIT LLC
For DFM/DFT, the best solution is to redesign the PWB and fill and cap (topside)each via being used as a test point - for bottom side probing, add a small semi-circular test land to the annular ring of each via and fill (no tent) with copper - ELIMINATE SOLDER FILL OF VIAS. This will create a convex land for source side probing unless a pealable masking or selective solder pallet is employed.

The problem with trying to optimize any wave process for this effort fights the physics and varying geometries of PTH from board to board and may require slower conveyor speeds than a non-dedicated setup allows (common practice off shore)- there is no via fill requirement by J-STD-001 or A-610 because of this issue.

The best via fill results I ever achieved was from a robotic selective solder fountain (not a wave) with one dire consequence - occasional copper dissolution of barrel shoulders of marginally constructed vias (poor black hole at mfg). At design - avoid using uncapped vias as test points - keep soldering out of that mix.
James Jauw, IPC-CIT, Stryker, USA

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