Vern Solberg and Ilyas Mohammed
San Jose, California USA
Stacking heterogeneous semiconductor die (memory and logic) within the same package outline can be considered for less
complex applications but combining the memory and processor functions in a single package has compromised test efficiency and overall package assembly yield. Separation and packaging the semiconductor functions into sections, on the other hand, has proved to be more efficient and, even though two interposers are required, more economical.
The separated logic and memory sections are configured with the same uniform outline for vertical stacking (package-on
-package). The most common configuration places the logic section as the base with second tier memory section soldered to a mating contact pattern.
This paper addresses the primary technological challenges for reducing contact pitch and package-on-package interface
technology. Research results will be presented that will illustrate multiple methods for forming smaller and finer pitch contacts on the base package section using existing wire-bond and transfer mold technology. The process developed utilizes copper bond-wire that enables several profile variations and can furnish an array configured contact pitch at or below 200m. The benefits are immediately seen.
This interconnect solution is very economical and lends itself to a wide variety of 3D packaging, including multiple-rows and area array, fan-in and fan-out, flat or step mold, bond wires present on bottom or top package, bottom package face-up or face-down die orientations.
Increasing demand for product miniaturization and high-performance computing continue to call for higher density devices and modules. The mobile electronics markets continue to see significant growth. Developers of UltraBook, smart phones and tablet products are now adopting multi-core processors and they need greater memory bandwidth. To meet these market trends, manufacturers are expecting faster process capability and greater memory bandwidth to be packed into less space with reduced power. Developers continue to design products that furnish greater functionality. Their goals often include reducing product size and weight.
To achieve the expanded functional capability, however, leads to adapting more complex and higher I/O semiconductors. The ideal package outline for many of these products will range between 10mm square to 14mm square. The semiconductor die outline and I/O requirement is often the primary limiting factor on the ultimate package outline dimensions. The 14mm square BVA package outline with 0.2mm contact pitch between the lower and upper PoP sections can accommodate up to 1440 I/O using the same amount of area currently required for a 288 I/O, 0.5mm pitch FBGA configured PoP.
Initially Published in the IPC Proceedings