Design for Manufacture and Test Using Thermal Cycling Under Bia



Design for Manufacture and Test Using Thermal Cycling Under Bia
There are many factors contributing to electrochemical failures on electronic devices including pitch, electrical field, ionic contamination and environmental conditions.
Analysis Lab

DOWNLOAD

Authored By:


Mark McMeen & Mike Bixenman
Magnalytix, LLC

Summary


There are many factors contributing to electrochemical failures on electronic devices including pitch, electrical field, ionic contamination and environmental conditions. Each of these factors is dependent on the installation location, with exposure to varying temperatures and humidity.

The interactions of all these factors are quite complex, and being able to predict potential electrochemical failures is challenging. A series of detection and preventive measures from the qualification of solder pastes to controlling the ionic contamination levels of the materials in production is needed.

The purpose of this research is to characterize this problem by varying humidity and temperature conditions. Humid heat simulates the thermal load of the components under test at high humidity levels with cyclic temperature conditions. C
Condensation tests verify the design, materials, and remaining electronic circuit residues' resistance to moisture.
The test methodology used for this research study will subject the test cards to humid heat and cyclic temperatures with frost conditions. The harsh environment simulates the thermal load including frost cycling to induce low dewing point conditions through cyclic temperature changes at high humidity. Humid environments challenge no-clean electronics and the basis for detecting electrochemical robustness at various points during the design validation testing.

Conclusions


The use of temperature cyclic with condensation is a unique test tool and protocol that is designed to put a number of variables into an accelerated format to find and uncover weaknesses in electronic assembly methods. This test is designed to find cleanliness issues as well as design issues and manufacturing process issues.

By using this multi variable test that uses both hot and cold thermal cycling to drive coefficient of thermal expansion (cte) ( -40 to 40c) and the introduction of frost and condensation into the test protocol aids in ionic mobility and high humidity moisture ingression. These conditions aids in the dew point condensation and frost condition. This is an extreme accelerated test to uncover and find weaknesses in material choices, process control, process parameters, and circuit card layout design and component package choices.

This Particular test DOE exposed the problem with via structures underneath BTC ( Bottom Terminated Components) by crating voids and blank space for frost and condensation to ingress into the area that we needed to be clean and minimize ionic movement and leakage currents. The idea of via structures for improving out gassing and minimizing unvolatized flux residues, which improves SIR results is quite proven as a good design rule. The vulnerability of ingression issues underneath BTC style components during thermal cyclic environments with frost and condensation shows the need for better test methodologies for design engineers to insure they address these potential failure modes in real fielded applications. This DOE was designed to explore the need to gather real test data and objective evidence to help develop new test protocols that better define BTC vulnerabilities and create a greater understanding of the variables that greatly impact BTC's.

SIR testing along with temperature cyclic testing with frost / condensation is a good tool in collecting beneficial data and objective evidence of what material sets, production parameters, and process control parameters, circuit design rules and component layout best practices to meet your fielded environmental objectives. SIR testing using specific real world components ( SIR Designed test components) in a test environment and in different circuit/component layout designs allows for determining and finding the weakest link in your design and which design gives you the best results from an SIR cleanliness objective before testing it in the final layout configuration. The more testing and objective evidence one can perform at the development and design stage the better the final design will work in a real fielded state because of the lessons learned on the front end.

This DOE showed how SIR test data in a non - thermal cyclic state all passed with SIR readings in the Log 10 and 11 range but once thermal cyclic testing with frost and condensation started then downward spikes and a drop in SIR was seen on the different designed circuit pad and via structures. Depending on your fielded application the use of SIR alone and in conjunction with thermal cyclic testing may better prepare and prevent latent warranty issues in production.

Initially Published in the SMTA Proceedings

Comments

No comments have been submitted to date.

Submit A Comment


Comments are reviewed prior to posting. You must include your full name to have your comments posted. We will not post your email address.

Your Name


Your Company
Your E-mail


Your Country
Your Comments