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PBGA Solder Stress Analyses Under Random Vibration

PBGA Solder Stress Analyses Under Random Vibration
Large size commercially available plastic ball grid array chip packaging was tested and analyzed under random vibration to assess its application feasibility on satellite electronics.
Analysis Lab


Authored By:

Yeong K. Kim, Ph. D., Seohyun Jang
Inha University
Incheon, South Korea

Dosoon Hwnag, Ph.D.,
Korea Aerospace Research Institute
Daejun, South Korea


Large size commercially available plastic ball grid array chip packaging was tested and analyzed under random vibration to assess its application feasibility on satellite electronics. Two types of the PBGA were chosen, and the chips were surface mounted without underfill on a daisy chained polyimide printed circuit boards. Two strong levels of the random vibrations were applied sequentially to investigate the sustainability of the PBGA chips mounted on the polyimide PCB with aluminum frame.

It was found that the test results did not show any solder failure under the test conditions, indicating the robust structural integrity and providing the evidences justifying the PBGA packaging application to the aerospace applications. Numerical analyses were also performed for the solder stress development mechanism. The results demonstrated that the first natural mode was not necessarily the dominant source for the maximum solder stress, and higher stress could be induced at higher natural modes depending on the chip size and its location.


In this study, the strong structural integrity of the PBGA chip packaging was verified by testing the PCB with sizable chips under the harsh random vibration tests. The results showed a possibility of the COTS part applications to the satellite electronics devices.

In the given frequency ranges of the vibration, the natural modes were calculated by the numerical modeling. Also, the quarter model was developed and effectively used to examine the detail stress development mechanism by calculating different cases. The calculation results showed that the maximum solder stress of the test sample model was found at the corner edge of the center chip mainly due to the 1st natural mode, which was in accordance with the usual expectation. However, the modified modeling calculations by changing the chip size and location represented that the maximum stress was found at the chip located apart from the center.

The unexpected results are from the stress development contributions of the higher natural modes than the 1st one, which have been frequently regarded as insignificant in the stress generation under vibration. In fact, in the modified sample calculation case, the 1st natural mode was found to be the least source of the maximum solder stress development. The results clearly demonstrated that, in the random vibration with the wide frequency range, the maximum solder stress location should be carefully investigated due to the fact that the dominant natural mode for the stress development is not necessarily the 1st one, and is dependent on the chip sizes and their locations.

Initially Published in the SMTA Proceedings


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