Advanced Substrate Technology for Heterogeneous Integration

Advanced Substrate Technology for Heterogeneous Integration
The development of semiconductor technology and multi-function demands of end products has driven IC foundry industry toward 7nm node process.
Analysis Lab


Authored By:

Yu-Hua Chen
Unimicron Technology Corp.


The rapid development of semiconductor technology and multi-function demands of end products has driven IC foundry industry toward 7nm node process, and even next generation of 5nm.[1] The I/O pitch of chip is reduced accordingly but the interconnection of build-up of IC carrier is still large to fit the IC interconnects (Fig. 1). In order to overcome the gap of I/O pitch between IC chip and carrier, the interposer technology has been considered as a solution to resolve the issue.

Challenge and needs for next generation interconnect Traditional semiconductor components include active chips, passive device, silicon interposer, organic substrate, and printed circuit board. How to package these components as a module is based on the product requirements. In recent decades, lots of assembly technologies and structure solutions for high density packaging (Fig. 2) have been evaluated, such as flip-chip assembly, Fan-out/Fan-in, InFo (Integrated Fan-out), CoWoS (Chip on Wafer on Substrate), SWIFT (Silicon Wafer Integrated Fan-out Technology), SLIM (Silicon-Less Integrated Module), EMIB (embedded multi-die interconnect bridge), 2.1D/2.3D/2.5D/3D IC packaging and so on. All of these package technology
solutions were considered to the electrical routing interconnection. The scaling of interconnection including trace and via is always the trend for the semiconductor industry supply chain.

High density interconnection trend To achieve the dimension scaling in IC substrate and PCB industry, glass as the removable carrier played a very important role for the next generation interconnection. Benefits to apply glass as the carrier[2] or substrate core[3,4,5] such as low profile surface suitable for high density application and good size effect for large form factor
compared with Si wafer had attracted many researchers’ attentions to develop. Besides, good dimension stability of glass also shows lower warpage in the process and high control level in fine line/space and via formation through traditional IC carrier and PCB process. However, there are still many challenges need to be overcome.


5G and AIoT are booming in next 5 years, US is in the leading position while China will be the strongest competitor in the markets.

Heterogeneous integration of high-end products existed from 2.5D planar interconnect (Si interposer, EMIB) to 3D die-to-die stacking (WoW, SoIC, Foveros).

Substrate technology is driven by extreme body size/high layer counts, heat dissipation, low loss material…etc. Investigating in long-term growth market and technology

Intensive CapEx for advanced package: 2.5D, EMIB, 3DIC, Chiplet, RDL SBT.

Fab-like substrate manufacturing will be coming soon.

Initially Published in the SMTA Proceedings


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