Fill the Void V - Mitigation of Voiding for Bottom Terminated Components

Fill the Void V - Mitigation of Voiding for Bottom Terminated Components
Voiding in solder joints is a complex issue. This paper focuses on solutions to voiding for commonly used bottom terminated components (BTCs).
Analysis Lab


Authored By:

Tony Lentz
FCT Assembly
Greeley, CO, USA

Greg Smith
BlueRing Stencils
Lumberton, NJ, USA


Voiding in solder joints has been studied extensively, and the effects of many variables compared and contrasted with respect to voiding performance. Solder paste flux, solder powder size, stencil design, circuit board design, via-in-pad design, surface finish, component size, reflow profile, vacuum reflow, nitrogen reflow and other parameters have been varied and voiding quantified for each. The results show some differences in voiding performance with respect to most of these variables, but these variables are not independent of each other. Voiding in solder joints is a complex issue that often requires multiple approaches to reduce voiding below required limits. This paper focuses on solutions to voiding for commonly used bottom terminated components (BTCs).

When voiding is an issue, it is often not possible to change the solder paste or circuit board design due to end user requirements and time constraints. It is much easier to change the stencil design and the reflow profile in an effort to reduce voiding, and this can be done in a timely manner. Stencil design and reflow profile can be used to minimize voiding for BTCs like Quad Flat No Lead (QFN) components. Optimization of the windowpane size and web width can help with voiding. Changing the volume of solder paste on the I/O perimeter pads of QFNs also has an effect on voiding. Use of linear ramp-to-spike (RTS) reflow profiles reduces voiding with some solder pastes, while ramp-soak-spike (RSS) profiles work better for other solder pastes. Stencil design and reflow profile were optimized for a variety of QFN components in order to minimize voiding. The results of this testing were quantified, summarized and recommendations given for ideal voiding performance.


Many of the variables that were tested influenced voiding. Several were found to reduce voiding and these are summarized below.

The linear ramp to spike (RTS) profile produced the lowest voiding as compared to the other profiles that were tested. This is expected and a normal result for the solder paste used in this work. Increasing the stencil foil thickness from 4 mils to 5 mils reduced voiding significantly. With the 5 mil thick stencil, 60% area of coverage produced lower voiding than the 70% area of coverage. Overall voiding area decreases as QFN component body size is increased. Overprinting the toe on the QFN perimeter (I/O) leads by 20 mils produces the lowest void area. This is true regardless of stencil thickness and area of coverage.

This work shows that voiding on QFN thermal pad solder joints can be significantly reduced using a low voiding solder paste along with the appropriate reflow profile. Void area can be further reduced through modifications to the stencil design by increasing stencil thickness or adding overprint to the toe of the perimeter (I/O) pads. It is recommended to work with your solder paste and stencil suppliers to reduce voiding to the lowest possible levels.

Initially Published in the SMTA Proceedings


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