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Effectiveness of I/O Stencil Aperture Modifications on BTC Void Reduction



Effectiveness of I/O Stencil Aperture Modifications on BTC Void Reduction
Many center pad voiding studies have focused on center pad footprint/stencil aperture designs. This study focuses on I/O pad stencil modifications.
Analysis Lab

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Authored By:


Carlos Tafoya, Gustavo Ramirez, Timothy O'Neill
AIM, Cranston, RI USA

Summary


Bottom terminated components, or BTCs, have been rapidly incorporated into PCB designs because of their low cost, small footprint and overall reliability. The combination of leadless terminations with underside ground/thermal pads have presented a multitude of challenges to PCB assemblers, including tilting, poor solder fillet formation, difficult inspection and - most notably - center pad voiding. Voids in large SMT solder joints can be difficult to predict and control due to the variety of input variables that can influence their formation.

Solder paste chemistries, PCB final finishes, and reflow profiles and atmospheres have all been scrutinized, and their effects well documented. Additionally, many of the published center pad voiding studies have focused on optimizing center pad footprint and stencil aperture designs. This study focuses on I/O pad stencil modifications rather than center pad modifications. It shows a no-cost, easily implemented I/O design guideline that can be deployed to consistently and repeatedly reduce void formation on BTC-style packages.

Conclusions


1) Voids were reduced to levels below 10% on all components. On the QFN48 component, the reduction of voids by increasing paste overprint on the I/Os is drastic. The largest void measured with +30 mils overprint (5.28%) is approximately the same size as the smallest void measured (5.22%) with the standard 1:1 print. The results of the cross-sectional analysis reveal a need to review all the devices at all overprint levels to understand how to balance voiding reduction with perimeter solder joint formation.

2) It appears that the temporary standoff generated by the I/O overprints raise the component to a height which promotes outgassing before wetting and collapse. The data in this experiment show height to be approximately 1- 1.5mils. Increasing the overprint and theoretical height to greater than 2mils does not provide considerable benefit and may result in undesirable outcomes.

3) Each package size responded differently. The smallest package did not appear to benefit from longer overprints as much as the larger packages did.

4) The impact of reflow profile on the void reduction effect is unclear as only one profile was tested. The profile used is considered the most challenging for void reduction and represents a common worst case scenario.



Initially Published in the IPC Proceedings

Comments

After hearing about this during conversations at the SMTA INT conference a few years ago, I tried it out. I have found this is an excellent method for void reduction on center pads. I have now used it across multiple assemblies and packages. You do need to look at your IO pads and work out the best overprint for each package and design, but it can be worth the effort.
Alan Woodford, NeoTech

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