Authored By:
Yan Ning, Michael H. Azarian, and Michael Pecht
Center for Advanced Life Cycle Engineering (CALCE)
University of Maryland, College Park, MD USA
Summary
The advancement of area-array packages, such as flip chips and chip scale packages, has driven the adoption of high density interconnects (HDIs) that allow for an increased number of I/Os with a smaller footprint area. HDI substrates and printed circuit boards use microvias as interconnects between conductor layers. HDIs have evolved from single-level microvias to stacked microvias that traverse sequential layers.
A stacked microvia is filled with electroplated copper to make electrical interconnections and support the outer level(s) of the microvia or components mounted to the upper capture pad. A common problem in copper-filled microvia fabrication is that the copper plating process can result in incomplete filling, dimples, or voids. However, the effects of these copper filling defects on the reliability of microvias are unknown. This study is the first known investigation and analysis of the influence of voiding and incomplete copper filling defects on the thermomechanical stresses in microvias.
Single-level and stacked microvias were modeled using the finite element method to simulate fully filled and partially filled microvias, as well as filled microvias with voids of different sizes. The stress states of these microvia models under thermal shock loads were investigated to determine the effects of the filling defects on the reliability of microvias.
The finite element modeling and simulation results demonstrated that stacked microvias experienced greater stresses than single-level microvias. With the same microvia geometry and material properties, copper filling reduced the stress level on the microvia structure, where fully copper-filled microvias had a lower stress level than partially filled microvias. The presence of voids generally increased the stress level in the microvia structure, but with a very small void size, the maximum stress in the microvia can be less than in a non-voided microvia. The stress level and the location of the maximum stress varied with changes in the void size.
Conclusions
A known failure mechanism in HDI substrates and PCBs is fatigue due to CTE mismatch between the dielectric material and metallization in a microvia structure. However, the effects of process-induced defects on microvia reliability were not studied in the past. FEA studies were conducted to investigate the influence of partial via filling and voiding conditions on the strain/stress distribution.
Different filling ratios (percentage) and voiding sizes in a microvia structure were examined in the research. Fully copper-filled microvias had a lower stress level than partially filled microvias, while the existence of voids was found to be not necessarily detrimental to microvia stress levels, depending on the void conditions.
(1) With the same microvia geometry and material properties, copper filling reduced the stress level on the microvia structure, where fully copper-filled microvias had a lower stress level than partially filled microvias.
(2) A small void can subtly reduce the thermomechanical stress in the microvia. As the void gets larger (within a threshold), the microvia structure is more compliant and results in even smaller stress. However, if the void size exceeds the threshold (the value of the threshold depends on many factors), the stress will start to increase.
The FEA studies provide insights regarding the effects of partial copper filling and plating voids on microvia reliability. Some of the results are not so intuitive or not reported in the past.
Initially Published in the IPC Proceedings
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