Authored By:
Chet A. Palesko, Amy J. Palesko
SavanSys Solutions LLC, Austin, Texas
James Haley, Catherine Shearer
Ormet Circuits, Inc., San Diego, California
Summary
As feature sizes are driven to be smaller, the cost of PCB fabrication is driven higher. In particular, sequential lamination of complex circuit boards is a time consuming and expensive process. However, industry expectations are for smaller, faster, and cheaper products.
In this paper, we present an alternative to sequential lamination for fabricating complex PCBs, where conductive paste is used as interconnect between cores. All costs associated with traditional methods and interconnect using conductive paste will be analyzed.
Conclusions
The use of a Z-interconnect layer with conductive paste vias is a cost effective alternative to copper plated microvias. The two cases analyzed showed that the addition of Z-Interconnect layers can be used to reduce total product cost. In both cases, this cost reduction was achieved through a variety of yield improvements as summarized below.
When using Z-interconnect layers with conductive paste instead of copper plated microvias (case 1), the need for sequential buildup layers is eliminated. The example in this paper is a 4-2-4 structure requiring four sequential lamination cycles compared to a single lamination cycle using Z-interconnect layers between 5 cores. Sequential lamination can cause significant yield loss; avoiding it improves the final yield.
When using Z-interconnect layers with conductive paste instead PTH vias (case 2), the final yield is improved by allowing more complete core testing before lamination and avoiding the need for high aspect ratio, low yield outer layer through hole drilling.
Initially Published in the IPC Proceedings
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