We are having issues with flux residues that are impacting in circuit and functional tests. After wave, we experience many incomplete readings due to flux residues on connector pins. Board Talk
Board Talk is presented by Phil Zarrow and Jim Hall of ITM Consulting.
With over 35 years experience in PCB assembly, Phil is one of the leading experts in SMT process failure analysis.
He has vast experience in SMT equipment, materials and processes.
A Lean Six-Sigma Master Blackbelt, Jim has a wealth of knowledge in soldering, thermal technology, equipment and process basics.
He is a pioneer in the science of reflow.
And welcome to Board Talk with Phil Zarrow and Jim Hall, The Assembly Brothers, pick and place who are also consultants with ITM Consulting. Yes, we can come to your facility. But here we are going to be answering some questions that our readers have sent in.
Today’s questions Jim is a flux residue question. This is from G.G. G.G. writes, we are having issues with flux residues that are impacting in circuit and functional tests. We use a no-clean flux that is applied by spray application. After wave, we experience many incomplete readings due to flux residues on connector pins. We have reduced the usage of flux to as low as possible and are still having the problem. Our test guy suggested brushing the connectors. Will that impact labor costs?
I am going to start off Jim by saying, this is just one of the little aspects of no-clean. We have to remember no-clean is not a material alone, it is a process. This is one of those things, when you are qualifying a no-clean process and a no-clean material, one of the things that you have to qualify and test for is in circuit test probe compatibility. The last thing you want to do is be cutting back your flux to the point where it is not performing well.
What we need to address here, is this is a specific material property of the no-clean flux. There are many different formulas of no-clean and they have different properties and they can be optimized for wetting, voiding and ICT testing. The flux formulas are designed to have residue that will have minimum interference with ICT.
You want to talk to your flux supplier. Find a flux formula that is designed to be compatible with ICT, in that it will leave a residue that will minimize these problems. Fortunately, the flux people have worked really hard with no-clean and they have made many improvements. So look at current formulations.
Unfortunately, nobody has come up with the perfect formula that does everything. There are always some trade-offs. Get a flux formula that the residue is very compatible with ICT. You may have to sacrifice some trade-off with some other property.
This really was the last frontier, the last boundary, of no-clean. When we look back historically, start would be the inception of no-clean in the very late 80s. There were errors, obviously cosmetics. We wanted to try to leave a residue that was acceptable and most important the performance of the residue in an SIR environment.
First off, did it solder? Did it wet adequately to give you good joists, in this case through-hole joists.
Yeah, exactly. Performance and now we look at is it compatible with the application that is going to be using. The most important test we use these days is SIR. The other area that was a tough one to overcome was making a material that leaves a residue that could be penetrated by ICT probes.
As Jim mentioned, there is a lot of work being done. We were involved in a project quite a few years ago with one of the solder paste companies, helping them design tests for this.
There are test probes, ICT test probes. The tips are designed to be better at penetrating no-clean residues.
That is another thing you can do in your ICT testing. Maybe you can substitute a different pin that will have a better chance of poking through that residue.
Again, this is another area where we have the combined pins with materials you are testing when you are doing a no-clean evaluation, a solder paste evaluation or a flux evaluation I should say too because here we are talking about wave, you want to basically test for compatible with ICT probes.
I know in the soldering analysis and the paste analysis that we do we include a test there and it is basically along the lines of a gauge R&R. There are several methods we use, but one method as a final method would be to actually take a batch of boards and test them. Repeatedly test them. Look and see how many false readings you get and that will kind of compare one material against another. But we have some other tests as well.
But regardless we are glad you joined us and thank you. We are always looking forward to the comments and reader input that you provide. As Jim said, you did waste a lot of valuable time listening to Phil and Jim, Board Talk.
But one very important lesson, regardless of whatever flux you are using and whether its probeable, please don’t solder like my brother.
And don’t solder like my brother.
No-clean fluxes is a basically a general term. So long you do not clean and it does not cause any issue on the reliability, it will term as no-clean flux. Therefore, no-clean fluxes ranges from low solid content to high solid content. Would suspect you are using rosin/resin with solid content 7 and above. This may result to residue on the board which is not properly cleaned off during wave process and thus causing some issue in the ICT testing. You may look for lower solid content flux which will give a clean board after your wave. Alternatively, look at your wave angle to create a better cleaning during soldering.
KHChew, Quantum Chemicals
Great topic this morning as these are the same types of questions we get regarding no-clean flux residues and difficult to test board finishes. The main issues we are finding is that some areas of the PCB will have heavier residues than others. This could depend on the temperature gradients across the board due to the spacing of connectors, components and such. But it also depends on the flux that flows onto and into the test points due to capillary action and pooling. This is one area where test vias are susceptible. They may partially fill or fully fill with flux which makes your sharp chisel tipped probe unable to penetrate the flux to make contact with the inner rim of the via. Your recommendation of using another tip is exactly the solution in many of these situations. Designs such as the sharp â€œblade or Razor" tip styles are able to contact the inner rim of the via without plunging into the flux.
This means that the probe will have its full spring force available to make contact with the test point unrestricted by the flux. Studies have shown that this approach often increases the First Pass Yields without adding spring force. In cases where this is not enough, High Preload spring designs will provide increased forces across the full travel of the test probe without having to go to the next higher spring forces which could put unwanted pressure on the PCB, test fixture and board supports.
Matt Parker, QA Technology Co. Inc.
As usual the flux is always the first thing to be blamed and usually 9/10 is nothing to do with the actual problem. Have you considered this maybe Plasticizers being released from under cured porous solder resist leaving a waxy/greasy residue over the bottom of the wave soldered board? No Residue/No Clean fluxes would normally leave a white powdery residue if GROSSLY sprayed and poorly processed. This will be easily broken down by ICT pins, Resist plasticizers will not as they are very sticky and not particularly volatile at the wave soldering temperatures. Very easy to find with the right chemistry but also a tell tale sign is a brown tar like substance by the wave former in the solder pot. When taken out it will be brittle and crumbly.
Gregory York, BLT Circuit Services Ltd
Inerting correctly the wave at solder pot with nitrogen, it is possible to decrease the flux consumption up to 40%. I see the flux reduction was already done by GG, but nitrogen atmosphere may "replace" certain amount of flux needed as protection at hot solder waves. In parallel of reducing ICT misjudge caused by flux dirt, the inerted wave may provide important reduction at dross formation (~80% less dross) and also, with better wettability, decrease overall defects up to 50% (barrel filling, much more, ~80% defects reduction)
Luiz Felipe Rodrigues, Air Liquide
The brothers have very adequately covered the options for non-conformance here. I have also experienced these excess application issues with ultrasonic flux sprayers. G G doesn't identify the type of flux sprayer he uses. The jist of the problem is that the sonic sprayers have a two stage power supply and if one of the stages goes down the control of the flux spayed goes out the window. Even if the volume of flux is turned down to zero.
Ike Sedberry, ISEDS
The problem begs the question, "Why would you NOT clean your boards?" Seriously. For a moderate to high level of reliability, Circuit Card Assemblies should be cleaned before parts are applied, and after each soldering process. Remove the contamination so that you have higher reliability. It is a simple, science-based, fact. In my opinion, the only types of assemblies that should NOT be cleaned, are low-value items, such as children's toys and ... not much else. Develop an efficient cleaning process, using either vapor defluxing in a modern vapor degreaser, or a water-based process for water-based fluxes, or even a bench top cleaning using a blended hydrocarbon with isopropanol, but remove the contamination, some how. Unless you are building toys for children.