Authored By:
Richard Boulanger, Jon Hander, Robert Moon, Richard Hollman
ASM NEXX
Billerica, Massachusetts
Summary
The migration to large panel substrates in advanced packaging applications is principally motivated by cost considerations. However, it is occurring at a time when package processing is becoming more complex and demanding. New package architectures featuring heterogeneous integration (HI), such as Intel's EMIB, TSMC's INFO, and many others, present challenging new requirements in the fabrication process. With feature sizes less than 10 microns, increasing number of patterned layers, and vias between layers, these demanding process steps must be realized on wafer and panel substrates alike.
The traditional equipment set for large panel substrates typically uses bulk processing and is not designed for wafer-like process requirements. Thus, a new class of process tool is required to bridge this technology gap, maintaining the economy of scale of large panel tools while meeting the requirements of current and future package architectures. For electroplating process steps, a vertical tool architecture running a single panel per process cell makes it possible to directly apply advanced wafer plating technology to panel substrates.
Individual panels are loaded in a rigid holder to minimize warpage and provide the large currents necessary for plating large areas. An overhead transport conveys the loaded panels to a series of cells which carry out the necessary steps in the deposition process. The initial step is a vacuum prewet, which prevents the occurrence of air bubbles in deep features when the panel is introduced into a plating bath. A series of plating cells allows a stack of different metals to be deposited in a single pass through the tool. Each cell is customized for a particular metal and, with features such as multiple anode zones and pattern-specific shields, can be customized for each device. Efficient agitation is also adapted from wafer plating tools to provide the fastest and best quality deposition processes.
This paper will show that the improvements in feature density, deposition uniformity and void free via filling that are required for heterogeneous integration can be achieved in large panel processing, providing the desired cost reduction relative to wafer processing for interposers and other package structures.
Conclusions
As traditional monolithic integration is being replaced by heterogeneous integration in electronic packaging, both silicon interposers and printed circuit boards (PCBs) are being considered. Silicon interposers exist today but are expensive (35- 40 cents per cm2 per layer). PCBs are less expensive but do not quite have the technology for the required interconnect density. We have demonstrated how a wafer plating tool can be reinvented to plate panels while achieving high density circuitry to reduce the costs and obtain unparalleled plating uniformity.
Initially Published in the SMTA Proceedings
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