Electronics Assembly Knowledge, Vision & Wisdom
Understanding PCB Design Variables That Contribute to Warpage
Understanding PCB Design Variables That Contribute to Warpage
To improve attachment yield rates, an evaluation several PCB design variables that are believed to contribute to warpage during reflow is proposed.
Analysis Lab

Analysis Lab programs cover topics including:
Corrosion, Contamination, Data Acquisition, ESD and EOS, Inspection, Measurement, Profiling, Reliability, R&D, RFID, Solder Defects, Test, Tombstoning, X-ray and more.
Submit A Comment
Comments are reviewed prior to posting. You must include your full name to have your comments posted. We will not post your email address.

Your Name

Your Company

Your E-mail

Your Country

Your Comment

Authored By:
Donald Adams, Todd MacFadden, & Rafael Maradiaga Bose Corporation
Framingham, MA, USA

Ryan Curry
Atlanta, GA, USA

PCB warpage has been identified as a possible contributor to unacceptable yield rates during reflow assembly of a module to a carrier board. The module has a land grid array pattern and is placed directly on solder paste on the carrier board. This results in low-profile solder joints which are sensitive to the coplanarity of both the module and the carrier boards. The typical failure mode is one or more solder joint opens caused by a lifted corner of the module after reflow.

In an effort to improve attachment yield rates, a design of experiment has been proposed to evaluate several PCB design variables that are believed to contribute to warpage during reflow, including: (1) laminate material, (2) layer-tolayer copper balance, (3) panel configuration of the 6-up module array and (4) location of the 6-up array in the PCB fabricator's working panel. To simplify the investigation, only the variables associated with module PCBs are considered; the carrier PCB design is held constant. Shadow Moire technique will be used to provide accurate warpage profiles of the 6-up module arrays before and after top- and bottom-side assembly, and again before and after attachment to the carrier board. A large volume of samples will be tested in order to gain statistical relevance of the data and correlate any yield problems to initial warp. The objective is to isolate the key design parameter(s) that contribute most to attachment problems.

Phase 1
The evaluation determined that the incoming PCB coplanarity had an impact on the yields of the assembly of the module to the carrier. Panels sorted into group a demonstrated a lower PPM than those in the B and C groups The PPM defect levels rose significantly in Group B and nearly doubled in Group C. Group A had a lower average coplanarity than those in Groups B and C. Despite the sorting the sorting at the panel level group a still had individual modules with high coplanarity values but at a lower percentage than the other groups.

Analyzing passing and failing modules PCB Coplanarity was found to have a statistical association to process yield. Passing modules were found to have a lower average coplanarity than failing modules.

In order to improve yields and eliminate board sorting improvements need to be made in the fabrication process by changing the design or material or a combination both.

Phase 2
Despite the consensus from PCB suppliers and the product development team the PCB material and copper balance had no statistically noticeable effect on the assembly yields. The balanced copper attribute may have been underrepresented due to the loss of the Supplier 1 samples and may warrant further investigation.

The board position in working panel was found to affect failure rate. Boards from non-corner locations displayed a better average coplanarity than those from the corners. This attribute may be difficult to change but will be investigated with PCB supplier.

Boards with more tabs located in the PCB corners were seen to have the largest impact to the carrier attachment success. Being a simple change to the panel this change can be easily implemented and monitored in larger lot sizes.

Initially Published in the SMTA Proceedings

No comments have been submitted to date.
Free Newsletter Subscription
Every issue of the Circuit Insight email newsletter will bring you the latest information on the issues affecting you and your company.

Insert Your Email Address

Directory Search

Program Search
Related Programs
bullet How to Manage Material Outgassing in Reflow Oven
bullet How Frequently Should We Recheck Profiles?
bullet Void-Free Soldering With Vapor-Phase Vacuum Tech
bullet What is the Life Span of a Profile Board?
bullet Evaluating Accuracy of Thermocouple Attach Methods
bullet How to Reduce Voiding on QFN Components
bullet Double Reflow-Induced Brittle Interfacial Failures
bullet Why Do Our Boards Warp During Reflow?
bullet Tips When Moving a Reflow Oven
bullet 5 vs 8-Zone Ovens
More Related Programs