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Fine Pitch CU Pillar with Bond on Lead Assembly Challenges for High Performance Flip Chip Package



Fine Pitch CU Pillar with Bond on Lead Assembly Challenges for High Performance Flip Chip Package
A technology featuring Copper Pillar Bond-On-Lead (BOL) with Enhanced processes delivers cost effective, high performance packaging solution.
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Authored By:


Nokibul Islam, Vinayak Pandey
STATS ChipPAC Inc
Fremont, CA, USA

KyungOe Kim
STATS ChipPAC Korea Ltd.

Summary


Fine pitch copper (Cu) Pillar bump has been growing adoption in high performance and low-cost flip chip packages. Higher input/output (I/O) density and very fine pitch requirements are driving very small feature sizes such as small bump on a narrow pad or bond-on-lead (BOL) interconnection, while higher performance requirements are driving increased current densities, thus assembling such packages using a standard mass reflow (MR) process and maintaining its performance is a real and serious challenge. Typical thermal compression bonding (TCB) using nonconductive paste can be used to mitigate the assembly risk up to certain extent of die size and package body size. On the other hand, the TCB process results in a significantly higher assembly cost due to very low throughput. The very cost sensitive consumer market is not quite ready to adopt TCB process for this reason.

To address the need for fine pitch Cu pillar Flip Chip, a technology featuring Copper Pillar Bond-On-Lead (BOL) with Enhanced processes, known as fcCuBETM, delivers the cost effective, high performance packaging solution that is required by the industry. BOL substrate technology with standard MR is becoming popular for high performance flip chip BGA (fcBGA) assembly. There are some papers in the literature that have addressed BOL or similar types of technology on small body size flip chip CSP type packages. However, none of the literature truly addresses the assembly challenges and risk mitigation plan for bigger body size fine pitch fcBGA packages. In this study a comprehensive finding on the assembly challenges, package design, and reliability data will be published.

Conclusions


Continuous trends in bump pitch reduction, performance improvement and Si node reduction, and the resultant move to ELK dielectrics, have created the need for a robust Flip Chip bump process that is serviced by the copper pillar technology. The fine pitch fcCuBE(R) technology evaluation for low cost consumer package has proved that the technology is very robust for assembly and performs exceptionally well through all critical JEDEC level reliability, and high current EM testing. The technology currently in high volume production for fcBGA and has excellent assembly yield and dppm level losses for opens/shorts.

Furthermore, the fcCuBE(R) technology now is extending beyond consumer markets as the SoCs undergo various application environments including rigorous automotive qualification program

Initially Published in the SMTA Proceedings

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