Electronics Assembly Knowledge, Vision & Wisdom
BTC-QFN Test Board Design for Qualifying Soldering Materials
BTC-QFN Test Board Design for Qualifying Soldering Materials
This research uses a non-standard test board with sensors placed at the bottom termination to study cleanliness and contamination effects under QFN components.
Analysis Lab

Analysis Lab programs cover topics including:
Corrosion, Contamination, Data Acquisition, ESD and EOS, Inspection, Measurement, Profiling, Reliability, R&D, RFID, Solder Defects, Test, Tombstoning, X-ray and more.
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Authored By:
Mike Bixenman, DBA
KYZEN Corporation
Nashville, TN, USA

Mark McMeen, Jason Tynes
STI Electronics
Huntsville, Al, USA

Summary
It becomes necessary from time to time to change materials of construction, manufacturing processes, and process conditions. A soldering material or cleaning agent may become unavailable due to environmental regulation, market forces, or reformulation. The following conditions necessitate validation and verification:

1. New soldering and / or cleaning materials changes that may improve performance or be more cost effective.
2. New soldering or cleaning equipment.
3. Technology assembly advances using a wide range of components placed in highly dense footprints. Each of these conditions require some form of verification and validation that the process meets the Original Equipment Manufacturers (OEMs) quality and reliability specifications.

J-STD-001 Requirements for Soldered Electrical and Electronic Assemblies states that validation and verification be confirmed with test vehicles that are representative of the product being produced. Many of the industry standard test vehicles are dated and not representative of current electrical and electronic assemblies. The purpose of this research is to use a non-standard test board with sensors placed at the bottom termination to study cleanliness and contamination effects under QFN components. The nonstandard test board has features to also study thermal paddle design options and to develop a risk profile. This research will report Surface Insulation Resistance effects at the source of the residue.

Conclusions
The focus of this paper was to build an understanding of flux residue entrapment and its potential to cause leakage currents under QFN components. QFN components have inherent challenges due to the large thermal mass of solder under the component termination, low standoff gaps and entrapment of heavy flux residue deposits. The non-standard site specific test vehicle provided the ability to study the effects of flux residue under the bottom termination and other key factors such as solder mask definition, reflow profiles, ground lug designs and cleaning effects.

Inferences from the data findings found that the driving factor for failure is absence of vent holes for solder flux residues to outgas at the center ground lug. When vent holes where placed in the center ground lug, residues could be present but did not cause failures. One could infer from these findings that when no-clean flux has a channel to outgas, the activity of the trapped level is less problematic. When flux residues do not have a channel to outgas, entrapped residues are active in nature and have a high potential to form leakage currents when the part is exposed to humid and moist conditions.

The data also indicates that improper cleaning can be problematic. Removal of flux residues under a low standoff part is high challenging. Longer wash time and pressure is needed to dissolve flux residues, create a flow pattern and totally clean under the component termination. When residues are totally cleaned, the risk of leakage currents is significantly reduced. Conversely, when residues are still present after cleaning, leakage current risks are elevated on components that did not have the vented thermal paddle.

The non-standard test vehicle design is an effective method for understanding residue effects and design options for developing a risk profile. The data findings can be used to optimize and develop best case conditions for improving the reliability of bottom terminated components assembled on printed circuit boards.

Initially Published in the SMTA Proceedings

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