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Young Laplace Equation Reveals New Possibilities Thermal Pad Design

Young Laplace Equation Reveals New Possibilities Thermal Pad Design
This paper shows how the application of the Young-Laplace equation can lead to an understanding of the soldering process of exposed pads and heat slugs.
Production Floor


Authored By:

Gunter Gera, Udo Welzel, Thomas Ewald, Harald Feufel
Robert-Bosch GmbH
Schwieberdingen, Germany


Driven by miniaturization and increasing power dissipation there is a strong need for better cooling of electronic components on printed circuit boards (PCB). One major contributor to the thermal resistance is the PCB itself. In IPC-7093 several thermal via configurations are discussed which enable the cooling of bottom terminated components through the PCB. The main risk of the designs is always the wicking of solder into the vias and the protrusion of solder on the opposite side of the PCBA. All suggested measures to avoid those risks are either not cost neutral (e.g. plugging) or thermally not optimized (e.g. solder mask) In this paper it will be shown how the application of the Young-Laplace equation (see original paper for equation) can lead to a thorough understanding of the soldering process of exposed pads (ePads) and heat slugs.

The use of via arrays without solder mask or plugging is suggested. It will be shown that solder wicking can be completely avoided by using an optimized land-pattern design. Due to conflicting targets the formation of solder protrusions can't be completely suppressed - though reduced down to a ppm-level. A slight modification of the electronic packages themselves will be proposed which is able to resolve this conflict.

With this technology thermal conductivities of up to 11700 (see original paper for equation) can be achieved. For an ePad with dimensions 8mm x 8mm this would result in an (see original paper for equation) of the PCB of only 1.33 see original paper for equation).


It has been shown that for ePads the failure modes solder wicking and solder protrusion, which can occur with failure rates of up to several percent, can be completely avoided by intelligent pad and component design. The radius of the thermal vias (see original paper for equation) should always be bigger than the maximum acceptable component standoff (see original paper for equation). In order to avoid the formation of solder protrusions buffer volume for excess solder has to be created. The best way to do so is to use components with groove structures at the bottom of the ePad. In order to avoid solder wicking into the grooves the width of the grooves should be at least two times the maximum component standoff, but still well below the diameter of the thermal vias.

This design enables a high degree of freedom for the placement of thermal vias. Due to the dense packing of vias mean thermal conductivities through the PCB of up to 62 (see original paper for equation) can be achieved. This could open up new possibilities for components with high power consumption which up till now had to use expensive technologies such as inlays, plugged vias, etc....

Initially Published in the SMTA Proceedings


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