Research
Innovative Panel Plating for Heterogeneous Integration
A Method to Investigate PCB Supplier Rework Processes and Best Practices
The Effects of PCB Fabrication on High-Frequency Electrical Performance
Aerosol Jet Printing of Conductive Epoxy for 3D
EOS Exposure of Components in the Soldering Process
High Thermo-Mechanical Fatigue and Drop Shock Resistant Alloys
Filling of Microvias and Through Holes by Electrolytic Copper Plating
NASA DOD Phase 2: Copper Dissolution Testing
MORE RESEARCH
Latest Industry News
How Telecom is Rolling Out 5G During a Pandemic
Can Software Performance Engineering Save Us From the End of Moore's Law?
Tech stocks have been a winning bet, but investors worry it will fade
All This Chaos Might Be Giving You 'Crisis Fatigue'
Notebook PCB makers to see tight capacity through 3Q20
How Effective Is Nano Coating On Stencils?
U.S. Critical Infrastructure Full of Security Holes
Auto Interior Is the New Exterior
MORE INDUSTRY NEWS

Surface Mount Warpage Case Study



Surface Mount Warpage Case Study
A quantity of surface mount packages were measured by shadow moire metrology to capture warpage levels, as they were heated through a reflow profile.
Analysis Lab

DOWNLOAD

Authored By:


Neil Hubble
Akrometrix

Jerry Young, Kim Hartnett
Micron Technology

Summary


Surface mount components are commonly evaluated for out-of-plane warpage levels across reflow temperatures. Decision making from these measurements is primarily based on signed warpage of a single component surface, per industry standards. However, signed warpage as a gauge can mislead users when surface shapes are complex, or direction of warpage is uncertain. The presented case study analyzes a range of common surface mount components for signed warpage. This wide ranging case study is used to create newly proposed methods for further defining and characterizing surface warpage in a quantitative manner.

Analysis of the case study data focuses on two related surface parameters: signed warpage Signal Strength and surface shape naming. Signal Strength is used to classify samples that are in "transition" between positive and negative warpage directions. New methods are shown to represent these transition areas in signed warpage graphs. Surface shape naming is used to further classify surface types, wherein correlation between shape name and surface mount defects are discussed. Algorithms for calculation of Signal Strength and classifying shape names are offered. Real world examples are used to determine appropriate thresholds for sign transitions and shape names in said algorithms. The study proposes a new, industry wide, approach to how companies present component warpage data.

Conclusions


A large quantity of surface mount packages were measured by shadow moire metrology to capture warpage levels, as the samples were heated through a reflow profile. Found warpage data was used to improve upon new methods of communicating surface shape, when dealing with large quantities of data.

JEDEC Full Field Signed Warpage (JFFSW) is already an often preferred gauge over the industry standard signed warpage, used by many industry leading companies, as the critical gauge for package warpage. This paper goes a step further in refining understanding of package shape, by introducing a new gauge, 3S Warpage. 3S Warpage not only classifies shapes as positive and negative, but also mathematically defines a third indeterminate category,labeled as a transition surface. This added category is designed to limit confusion in summarizing package 3D surface shape with a single gauge.

Packages from the case study were also assigned a shape name, established by newly established algorithms. Shape naming algorithms were improved through an iterative process, when compared with qualitative shape assignments. The shape name adds a new variable that can be tracked and correlated over time with surface mount attachment reliability and surface to surface mating. These shape names can be used in establishing package trends and for further, future understanding of assembly yield based upon package warpage.

Initially Published in the IPC Proceedings

Comments

No comments have been submitted to date.

Submit A Comment


Comments are reviewed prior to posting. You must include your full name to have your comments posted. We will not post your email address.

Your Name


Your Company
Your E-mail


Your Country
Your Comments



Board Talk
How Effective Is Nano Coating On Stencils?
What Causes Board Delamination?
01005 Component Challenges and Bugs
Sticky Residue Under Low Clearance Parts
Soldering Relays Intrusively in Lead Free Process
Printing vs. Dispensing
Maximum Board Temperature During Tin-Lead
Is There a Spacing Spec for SMD Components?
MORE BOARD TALK
Ask the Experts
Recommended Fiducial Shape
HASL vs. Immersion Gold
Very Low Temp PCBs
Looking for Long-term Component Storage Options
Baking After Cleaning Hand Placed Parts
Conformal Coating Recommendation
Burned Chip Repair
BGA Component Grounding Problem
MORE ASK THE EXPERTS