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Expanding IEEE Std 1149.1 Boundary-Scan Architecture
Expanding IEEE Std 1149.1 Boundary-Scan Architecture
This paper discusses the expanded use of boundary-scan testing beyond the typical manufacturing test to capture structural defects.
Production Floor

Authored By:
Jun Balangue
Keysight Technologies
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Summary
This paper will discuss the expanded use of boundary-scan testing beyond the typical manufacturing test to capture structural defects on a component/devices in a printed circuit board assembly (PCBA).
The following topics will be discussed to demonstrate the capability of boundary-scan test system on how we can extend beyond typical manufacturing test:

1. Boundary-scan as a complete manufacturing test system - A boundary-scan test system should be able to cover all the needs of a manufacturing test to be an effective solution.

2. Boundary-scan implementation during PCBA design stage - This topic will discuss the importance of design for test (DFT) at the early stage of PCBA design to maximize the use of boundary-scan to lower the cost of test while increasing the test coverage.

3. Implementation of boundary-scan beyond typical structural testing - While capturing structural defects are important during manufacturing test, the need for boundary-scan to include other areas beyond PCBA structural testing is now necessary.
Conclusions
Boundary-scan tools are now capable to interpret and convert the binary files or configuration (CFG) files supplied by the ASIC designer or vendor to execute Built-in self-test (BIST) such as memory BIST, Logic BIST and other custom function test that will help extend the coverage of a board during boundary-scan testing.

The boundary-scan 1149.1 along with the new enhancements and standards such as - IEEE 1149.6 and IEEE 1687 will redefine the testing strategy for PCBA, not only in the In-Circuit Test but including various areas of manufacturing such as - functional test, burn in and repair as well as the prototype and NPI stages of the product which will help the industry in ensuring testability of the next generation of PCBAs and streamlining the efficiency of the test systems.
Initially Published in the IPC Proceedings
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