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Stencil Pattern for Thermal Pads on QFNs
We know why it is important to "mesh" but need more info regarding what is best aperture size, number of apertures, etc. Can you point us to information?
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Stencil Pattern for Thermal Pads on QFNs
We need more information regarding the stencil pattern for thermal pads on QFNs. We know why it is important to "mesh" but need more info regarding what is best aperture size, number of apertures, etc. Can you point us to information?
C.P.
Expert's Panel Responses

Although, a little dated, the IPC has published a document from which some basic recommendations can be gleaned.

IPC-7093 - Design and Assembly Process Implementation for Bottom Termination Components

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Eric Bastow
Senior Technical Support Engineer
Indium Corporation
Eric is an SMTA-certified process engineer (CSMTPE) and has earned his Six Sigma Green Belt from the Thayer School of Engineering at Dartmouth College. He is also a certified IPC-A-600 and 610D Specialist. He has an associate's degree in Engineering Science from the State University of New York and has authored several technical papers and articles.

QFNs, like all devices, are designed with electrical, mechanical and thermal requirements in mind. The enlarged "ground" pad on the bottom of the QFN is engineered not only to provide the electrical connection but also to aid in dissipation of thermal energy to the underlying copper plane. It is important to follow the IC vendor's recommendation for the amount of solder or solder paste required on the underside of the device and for all other solder connections on the package.

Ensure that if you "mesh" (I assume you mean provide "window pane" layout under the device to aid paste outgassing) the pattern compensates for the lack of paste in the pane frame areas ("streets"). Also make sure that the volume of paste under the QFN doesn't buoy the device too high so as to cause opens or poor solder joints on peripheral connections. Without knowing exact device size, contact patterns and PCB layout, it is impossible to recommend aperture size details for your application. Always start with the IC package manufacturer's technical data sheet for the solder paste requirements and optimize from there. Your finished pattern should closely approximate what is recommended in the data sheet in order to meet reliability requirements for that particular QFN.

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Gary Freedman
President
Colab Engineering
A thirty year veteran of electronics assembly with major OEMs including Digital Equipment Corp., Compaq and Hewlett-Packard. President of Colab Engineering, LLC; a consulting agency specializing in electronics manufacturing, root-cause analysis and manufacturing improvement. Holder of six U.S. process patents. Authored several sections and chapters on circuit assembly for industry handbooks. Wrote a treatise on laser soldering for Laser Institute of America's LIA Handbook of Laser Materials Processing. Diverse background includes significant stints and contributions in electrochemistry, photovoltaics, silicon crystal growth and laser processing prior to entering the world of PCAs. Member of SMTA. Member of the Technical Journal Committee of the Surface Mount Technology Association.
There are some basic rules for QFN pad arrays. A widely used one is to use square pads of 1 mm to 2 mm in length and to provide a distance between these pads of 0.4 mm. Your stencil house should be able to help you more on your specific components.
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Edithel Marietti
Senior Manufacturing Engineer
iDirect
Edithel is a chemical engineer with 20 year experience in manufacturing & process development for electronic contract manufacturers in US as well as some major OEM's. Involved in SMT, Reflow, Wave and other assembly operations entailing conformal coating and robotics.
Recommended aperture design for QFN thermal pads is 40-50% reduction of paste printed using window pane pattern. Also to try to keep paste out of open via's.
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Bill Coleman
Vice President Technology
Photo Stencil
For over 18 years, Dr. Coleman has been the vice president of technology for Photo Stencil, working closely with customers to understand their printing requirements. His efforts have resulted in several new stencil products.

There is no one size fits all for thermal pads on QFN's. This is going to depend on the package, size of the thermal pad, board thickness, number of via's etc.

Some component suppliers will have stencil design guidelines in the data sheet for the specific part. You will need to verify the volume of solder is correct.

If you cannot find stencil guidelines for your particular part, you may have to try looking at a part with a similar package design and thermal properties. Also most stencil suppliers are familiar with these guidelines, they may help as well.

Hope this helps.

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Brien Bush
Manufacturing Applications Specialist
Cirtronics Corp.
Mr. Bush has 20 years experience in electronics contract manufacturing. Major areas of expertise include through hole, SMT, wave and selective soldering.
It is recommended to reduce the perimeter of the ground pad slightly before making additional modifications. Once the perimeter is reduced (I suggest a minimum of 0.0025" per side), create a pattern that results in 65-70% coverage of the remaining area. Square apertures with a radius at the corner is recommended for optimal paste release. It is also good practice to design the pattern around open via's to allow for out gassing.
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Stephanie Nash
Director
Integrated Ideas & Technologies, Inc.
Stephanie Nash is the Director of Technical Services & Marketing for Integrated Ideas & Technologies, Inc., a premier manufacturer of SMT stencils. She has been instrumental in the stencil design and technical support.

We recommend reducing the total printed paste area to 50-60% of the ground pad based on the board copper layer and using 5 round apertures who's combined volume adds up to 50-60%. These aperture sizes will change with the size of the ground pad on the QFN, e.g. larger ground pads require larger printed paste dots.

We call this pattern a 5-dice pattern because the printed solder paste looks like the dots on dice. This pattern allows for maximum gas escape routes in order to minimize the potential for voiding.

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Tony Lentz
Field Applications
FCT Assembly
Tony has worked in the electronics industry since 1994. He worked as a process engineer at a circuit board manufacturer for 5 years. Since 1999, Tony has worked for FCT Companies as a laboratory manager, facility manager, and most recently a field application engineer. He has extensive experience doing research and development, quality control, and technical service with products used to manufacture and assemble printed circuit boards. He holds B.S. and M.B.S. degrees in Chemistry.

IPC 7525 should give you everything that you need to know about apertures design.

Now, for your particular case, this spec has more details: IPC-7093 standard, "Design and Assembly Process Implementation forBottom Termination Components".

On the same time take in consideration the new stencil manufacturing technologies that provide increased paste release.
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Georgian Simion
Engineering and Operations Management
Independent Consultant
Georgian Simion is an independent consultant with 20+ years in electronics manufacturing engineering and operations.
Contact me at georgiansimion@yahoo.com.

IPC 7525, details aperture designs for QFN's. However PCB DFM will allow you to make to calculate this correct volume requirement.

General rules are as follows,

50% to 60% reduction to allow the component to solder and not float during reflow.

Meshing can be done in any shape provided scopping will not occur.

Avoid using large thermal via's in your design. If large via's are required then calculate the volume required to fill the via hole plus the 50% required for the soldering of the terminal plane.

Some via's can be plugged by your PCB manufacture, make use of this. If you are unsure, contact; Asahitec Stencils Pvt.Ltd., www.asahitec.in for any stencil DFM and stencil manufacturing. they are the best in providing DFM input for your product.

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Kishan Sarjoo
Process Engineering Manager - Electronics
Altech UEC, South Africa
Currently with Altech UEC and responsible for technology road map in PCBA electronic manufacturing and technical support for PCBA electronic manufacturing for Altech UEC and its JDM's. Over 7 years in SMT, Radial Insertion, Wave solder & Test Applications.
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