Electronics Assembly Knowledge, Vision & Wisdom
New Approaches to Develop a Scalable 3D IC Assembly Method
New Approaches to Develop a Scalable 3D IC Assembly Method
In this paper, we will discuss various assembly options and the challenges posed by each.
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Authored By:
Charles G. Woychik Ph.D., Sangil Lee, Ph.D., Scott McGrath, Eric Tosaya and Sitaram Arkalgud Ph.D.
Invensas Corporation
San Jose, CA

Summary
The challenge for 3D IC assembly is how to manage warpage and thin wafer handling in order to achieve a high assembly yield and to ensure that the final structure can pass the specified reliability requirements. Our test vehicles have micro-bumped die having pitches ranging from 60um down to 30um. The high density of pads and the large die size, make it extremely challenging to ensure that all of the micro-bump interconnects are attached to a thin Si-interposer. In addition, the low standoff between the die and interposer make it difficult to underfill.

A likely approach is to first attach the die to the interposer and then the die/interposer sub-assembly to the substrate. In this scenario, the die/interposer sub-assembly is comparable to a monolithic silicon die that can be flip chip attached to the substrate. In this paper, we will discuss various assembly options and the challenges posed by each. In this investigation, we will propose the best method to do 2.5D assembly in an OSAT(Outsourced Assembly and Test) facility.

Conclusions
The semiconductor fabs can produce robust and reliable devices with TSVs.

A PF3 type of process, is compatible with an OSAT facility, and can produce 3D IC packages that can meet the challenges of JEDEC reliability specifications.

This work has shown that a high yielding MBD to Si-ITP process is achievable.

The manufacturing infrastructure exists to assembly in high volume these types of packages using existing OSAT manufacturing infrastructure.

Initially Published in the IPC Proceedings

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