Electronics Assembly Knowledge, Vision & Wisdom
Solder Paste Stencil Design for Optimal QFN Reliability
Solder Paste Stencil Design for Optimal QFN Reliability
In this study, the volume of solder used in assembly of QFNs was varied to investigate the relationship between standoff height and thermal cycle life.
Production Floor

Authored By:
B. Gumpert
Lockheed Martin, Ocala, FL USA
,{url:'http://www.circuitinsight.com/videos/programs_final.mp4'}], clip:{autoBuffering:true, autoPlay:true, scaling:'scale' } }).ipad();
Summary
The use of bottom terminated components (BTC) has become widespread, specifically the use of Quad Flat No-lead (QFN) packages. The small outline and low height of this package type, improved electrical and thermal performance relative to older packaging technology, and low cost make the QFN/BTC attractive for many applications.

Over the past 15 years, the implementation of the QFN/BTC package has garnered a great amount of attention due to the assembly and inspection process challenges associated with the package. The difference in solder application parameters between the center pad and the perimeter pads complicates stencil design, and must be given special attention to balance the dissimilar requirements.

The lack of leads on the QFN/BTC package and the low standoff height result in significantly less compliance relative to other package types, making the QFN/BTC package more susceptible to CTE mismatch issues. Careful assembly of QFNs and proper printed circuit board (PCB) design can result in acceptable reliability depending on the overall design. One area that has not been well addressed, however, is the impact of die to package size ratio, and how this factor should be considered in circuit card assembly. IPC-7093 mentions the inverse relationship between relative die size and reliability, and Syed and Kang found the relationship to be non-linear, yet die size is seldom noted in component datasheets, and vendor recommendations do not include this ratio as a factor in assembly.

In this study, the volume of solder used in assembly of two QFN/BTC packages will be varied to investigate the relationship between standoff height and thermal cycle life, and to determine acceptable process limits with respect to first-pass yields. The QFNs selected have dissimilar die to package size ratios to assess the impact of this factor on the process window. Solder joint defect levels and thermal cycle results will indicate the ability to adjust manufacturing parameters to achieve a balance between the two objectives of process yield and reliability. The results will define a process window that provides the optimal installation of these packages.
Conclusions
Two QFN/BTC packages were installed onto representative circuit cards using a variety of solder paste applications. Many of the standard guidelines for QFN/BTC application and soldering were followed, with only the solder paste volume adjusted to control the resulting solder joint height and geometry. Actual solder joint height for this assembly was shown to correlate well to expected solder joint height according to the stencil design.

In general, an increase in the amount of solder paste used resulted in an increase in the amount of voiding. This is expected, as the pathways for volatiles to escape are reduced and the overall amount of volatiles is increased as the total solder volume increases. Voiding was low in general, with few instances of voiding exceeding 25% of the soldered area.

Thus far, the failure rates for the various solder joint configurations (height) are not as predicted by the simulation software. Of particular note is the inconsistency of the solder joints on the QFN68 packages at increased solder joint heights. The joints seen in the Figure 8 above make electrical connection, but may represent weak joints that are likely to fail relatively early. This joint variation in the previous testing could have skewed the simulation baseline, and therefore the current prediction, which likely assumes that every joint is exactly the same within the programmed parameters.

Another potential impact that could be impacting thermal cycle survivability is the slight change in the solder joint shape at the toe fillet. The solder stencil was adjusted to vary the amount of solder paste applied at the perimeter pins, resulting in solder joints that had very similar geometry, but which were not exactly the same. The slightly larger solder joints on the locations with a shorter solder joint height could improve the thermal cycle survivability. The simulation software did not allow the size or shape of the toe fillet to be adjusted.

Until more failure data is collected, specific conclusions cannot be substantiated, but the observations and results so far indicate that center pad size (and presumably die to package ratio) should not be ignored when implementing QFNs. There were clear differences in the results between the two packages used in this study. Components with a small center pad are relatively robust not only in thermal cycling, but also with respect to yield and consistency in the manufacturing process.

Components with a large center pad require more attention, as they have a smaller process window for optimal solder joints, and have reduced reliability. Initial results indicate that such a component is best installed with 50% or more in solder paste reduction on the center pad, but more failure data is required to determine the ideal stencil design.
Initially Published in the IPC Proceedings
Submit A Comment

Comments are reviewed prior to posting. Please avoid discussion of pricing or recommendations for specific products. You must include your full name to have your comments posted. We will not post your email address.

Your Name


Company


E-mail


Country


Comments


Authentication

Please type the number displayed into the box. If you attempt to submit information and receive an error, you may need to refresh the page and insert the information again.



Related Programs
bullet Returning to Basics in the SMT Screen Printing Process
bullet Minimizing Voiding in QFN Packages
bullet Press Fit Roadmap for High Performance Process
bullet The Challenges of LGA Server Socket Trends
bullet 3D Assembly Processes a Look at Today and Tomorrow
bullet Low-Silver BGA Assembly
bullet Selecting Stencil Technologies to Optimize Print Performance
bullet What is the Best Way to Clean Solder Stencils?
bullet Optimization to Prevent the Graping Effect
bullet Issues with BGA Components Near PCB Edges
More Related Programs
About | Advertising | Contact | Directory | Directory Search | Directory Submit | Privacy | Programs | Program Search | Sponsorship | Subscribe | Terms

Circuit Insight
6 Liberty Square #2040, Boston MA 02109 USA

Jeff Ferry, Publisher | Ken Cavallaro, Editor/Business Manager

Copyright © Circuitnet LLC. All rights reserved.
A Circuitnet Media Publication