Electronics Assembly Knowledge, Vision & Wisdom
Reliability of Stacked Microvia
Reliability of Stacked Microvia
Study was designed to understand the reliability of Type 1, 2, and 3 Microvias. The reliability test coupons included four stacks of microvias and a buried via.
Production Floor

Production Floor programs cover topics including:
CAD/CAM/CIM/EDA, Circuit Board Handling, Clean Room, Cleaning Operations, Component Insertion, Component Prep, Dispensing, Feeders, Fume Extraction, Hand Tools, Labeling/Marking, Lasers, Material Handling, Odd Form, Ovens/Curing, Packaging, Stencil Printing, Repair/Rework, Soldering and more.
Authored By:
Hardeep Heer, Ryan Wong
FTG Corp.

Reliability of Microvia has been a concern since microvias were introduced to our industry. This study was designed to understand the reliability of Type 1, Type 2, and Type 3 Microvias. Reliability Test Coupon design was developed in co-operation with PWB Interconnect to include up to four stacks of microvias placed on and off a buried via. Standard FR4 material, meeting the requirement of IPC-4101/24, was selected and IST thermal cycling was chosen as a reliability test method.

Staggered microvias were not considered because previous testing has shown that staggered microvias are as reliable as single stage microvias. It was also decided to have all the microvias plated shut during the copper plating process. Samples were produced as one lot, utilizing FTG's standard manufacturing processes. Efforts were made to include all possible test conditions required to understand microvia reliability.

This study was a preliminary study and the objective was to understand the behavior and reliability of stacked microvias based on the number of stacks, the pitch between the vias and the effect of stacking microvias on a buried via compared to off a buried via. A secondary objective was also to understand FTG's manufacturing process for multiple stacked microvias, since this is not yet a typical design requirement in the Aerospace and Defense industries.

The test data shows that stacked microvias placed on a buried via are in themselves as reliable as stacked microvias off the buried via. Although Sense B data shows a higher failure rate, it is believed that the failure mode is related to the buried via and material degradation rather than a microvia failure. Two-stack microvias located on buried vias performed worse than the other on-buried via structures, but it is hypothesized that this is caused by the longer barrel length of the buried via in the board design.

The length of barrel of buried vias has a higher degree of effect on the IST results for test temperatures above the Tg of the laminate. Shorter buried vias are more reliable even when operating at temperatures above the Tg of the material. Increasing the number of lamination cycles and higher pre-conditioning temperature also contributed to a higher degradation effect on standard laminates.

Increasing the number of stacks did not appear to have a major effect on failures. Although resistance increased nominally in Sense A measurements, the reliability of the microvias generally was maintained below the resistance change threshold. However, the number of stacks introduces registration challenges during the manufacturing process. A robust registration system is required to ensure that the microvias are registered in a controlled manner to reduce variation that can result in poor connectivity to the underlying plated shut microvia. Reducing via pitch from 1.0mm (0.04") to 0.8mm (0.032") also had a marginal effect on reliability.

A conventional IST cycling temperature to test microvias may not be the optimal temperature to test microvia reliability. Resistance changes of greater than 10% should be the failure criteria after pre-conditioning. A gradual rise in the resistance change plot is an indication of degradation of the material and is not necessarily indicative of avia failure. Further testing will be required to understand the effect on microvias when resistance is gradually increasing above the 10% threshold. This study also showed that the selection of material is critical to product reliability. If the circuit board application demands performance under temperatures higher than the material's Tg, then a material with a higher Tg should be selected.

This was a preliminary study to investigate the general reliability of stacked microvia structures. The number of variables being evaluated required a significant number of test coupons. This resulted in limiting the sample size for higher temperature cycling. With these results and observations on test temperatures and failure modes, further testing with a narrowed scope can be completed to determine statistically proven reliability of different microvia structures. This study has provided a foundation of knowledge that can be built upon by a multitude of testing in the future.

Initially Published in the IPC Proceedings

No comments have been submitted to date.
Submit A Comment
Comments are reviewed prior to posting. Please avoid discussion of pricing or recommendations for specific products. You must include your full name to have your comments posted. We will not post your email address.

Your Name






Please type the number displayed into the box. If you receive an error, you may need to refresh the page and resubmit the information.

Related Programs
bullet Challenges for Selecting Appropriate TIM2 Material for CPU
bullet Filling of Microvias and Through Holes by Electrolytic Copper Plating
bullet High-Speed 3D Surface Imaging Technology in Electronics Manufacturing
bullet Additive Manufacturing Printed Circuit Board Assembly Processes
bullet Selective Solder Paste Printing for BGA Components
bullet Reliability of Stacked Microvia
bullet Issues With SMT Component Alignment
bullet Advanced Printing for Microelectronic Packaging
bullet Larger Stencil Apertures and Type 4 Paste
bullet Printing of Solder Paste - A Quality Assurance Methodology
More Related Programs