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Board  Processes and Effects on Fine Copper Barrel Cracks
Board Processes and Effects on Fine Copper Barrel Cracks
This research is to determine if there is a relationship between PCB fabrication processes and the prevalence of fine barrel cracks.
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Authored By:
Edward Arthur, Charles Busa, Melissa Durfee, Chad Gibson, Wade Goldman P.E.


Summary
The onset of copper barrel cracks is typically induced by the presence of manufacturing defects. In the absence of discernible manufacturing defects, the causes of copper barrel cracks in printed circuit board (PCB) plated through holes is not well understood. Accordingly, there is a need to determine what affects the onset of barrel cracks and then control those causes to mitigate their initiation.

The objective of this research is to conduct a design of experiment (DOE) to determine if there is a relationship between PCB fabrication processes and the prevalence of fine barrel cracks. The test vehicle used will be a 16-layer epoxy-based PCB that has two different sized plated through holes as well as buried vias.

The DOE will include an 8 run experiment with 2 center point runs for a total of 10 runs. This experimental setup is a half fractional factorial with resolution IV. Resolution IV means that main effects, each factor considered individually, are confounded with 3-way interactions. The PCB manufacturing processes selected as factors include laminate cooling rate, plating current density, pulse waveform, and hot air solder leveling (HASL) reflow.

A confounded interaction cannot be separated out statistically from its "aliased" main effect. This DOE is a screening design, which is preferred for early investigation since the likelihood that a 3-way interaction would dominate over a main effect is extremely unlikely.

For this DOE, some deviations from an ideal experimentation setup are present. Since each coupon has multiple holes, samples are not uniquely independent. Also, the factors of pulse waveform and current density are not independent. The pulse waveform is also a nominal variable listed as a continuous factor for design purposes and has no center point value.

Conclusions
The research identified PCB fabrication processes that were significant contributors to not only the incidence of cracks but also the length of cracks, in copper plated vias, after exposure to thermal shock excursions. Statistical analyses of the resultant DOE data identified the optimal settings for the four factors selected from the PCB fabrication processes.

The binary logistic regression indicated that the likelihood of cracking increased from 220% to 561% across all via types when changing from water laminate cooling to air cooling within the same number of HASL reflow cycles. Since the plating is performed after the laminate cooling process, the influence of the laminate cooling process on the likelihood of cracking is not readily apparent. Also, as the number of HASL reflows increased, the likelihood of crack occurrence increased from 25% to 77% across these via types, when holding the laminate cooling method constant.

These results support the optimal recommendations of water cooling with HASL reflow of 1, as presented in Table 3.
For 457.2 μm PTH, the only significant factor affecting crack length was the HASL reflow.. For the 635 μm PTH, HASL reflow was also the most significant factor on the length of barrel cracks. Other significant factors included current density and the second-order interaction effect between the laminate cooling method and current density. Figure 3 response slopes suggested a current density setting of 8 would reduce crack length and standard deviation, notably due to the interaction plot shown in Figure 14, where a setting of 14 coupled with standard water cooling should be avoided.

For buried vias, laminate cooling method (air) was the most significant factor affecting the length of barrel cracks, even though the plating is performed after the laminate cooling process. Pulse waveform setting of 1 was the second most significant factor. Other significant factors included the second-order interaction effect between the laminate cooling method and current density, shown by Figure 17 and Figure 18, for the crack length average and standard deviation, respectively. This interaction effect further substantiated the optimal recommendations of standard cooling with current density 8, as presented in Table 3.

While the DOE was being conducted, the no-crack thermal shock requirement was reviewed for applicability against service life requirements. Multiple PCB coupon samples underwent close to 100 thermal shock cycles to determine when cracks initiated and to estimate crack growth rates. Engineering models estimated the service life correlating with 100 thermal cycles. This effort resulted in a relaxation of the crack criteria to allow up to 20% crack length of the specified minimum wall thickness.

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