A new integrated circuit patterned onto a sheet of graphene offers the possibility for flexible, ultra-energy-efficient, and transparent electronics. Technology Briefing
Transcript
Researchers at UC Santa Barbara have designed and modeled an
integrated circuit scheme in which transistors and interconnects are
monolithically patterned seamlessly onto a sheet of graphene. The
demonstration offers possibilities for flexible, ultra-energy-efficient,
and transparent electronics.
Today's dominant technology, CMOS transistors and metal
interconnects, pose fundamental challenges in continuously shrinking
their feature-sizes and suffer from increasing "contact resistance"
between them; both of these characteristics lead to degrading
performance and rising energy consumption.
Graphene-based transistors and interconnects are a promising
nano-scale alternative that could potentially address these issues. Why? In addition to its atomically thin and pristine surfaces, graphene
has a tunable band gap, which can be adjusted by lithographic sketching
of patterns; that is, narrow graphene ribbons can be made
semiconducting, while wider ribbons act like metal.
Hence, contiguous graphene ribbons can be configured from the same
starting material to create both active and passive devices in a
seamless fashion, with lower interface and contact resistances.
As they described recently in the journal Applied Physics Letters,
the UC Santa Barbara group pioneered a methodology using the
Non-Equilibrium Green's Function (or NEGF) to evaluate the performance
of complex circuit schemes.
The all-graphene circuits have achieved 1.7X higher noise margins and
1-2 orders of magnitude lower static power consumption over current CMOS
technology.
