Research
Innovative Panel Plating for Heterogeneous Integration
A Method to Investigate PCB Supplier Rework Processes and Best Practices
The Effects of PCB Fabrication on High-Frequency Electrical Performance
Aerosol Jet Printing of Conductive Epoxy for 3D
EOS Exposure of Components in the Soldering Process
High Thermo-Mechanical Fatigue and Drop Shock Resistant Alloys
Filling of Microvias and Through Holes by Electrolytic Copper Plating
NASA DOD Phase 2: Copper Dissolution Testing
MORE RESEARCH
Latest Industry News
Smartphone Shipments to Plummet 11.9% in 2020
PC market to dip 7% this year
Alternate Roads to Flexible Electronics
Huawei hid business operation in Iran after Reuters reported links to CFO
Global Distributor Group Tackles Tariff Inefficiencies
How to Set Boundaries While Working Remotely
Apple must face U.S. shareholder lawsuit over CEO's iPhone, China comments
The AI-Based Competitive Revolution
MORE INDUSTRY NEWS

Silicon V-Groove Alignment Bench for Optical Component Assembly



Silicon V-Groove Alignment Bench for Optical Component Assembly
In this paper, a Silicon Interposer is described that provides electrical interconnects to an edge emitting laser die and a laser monitor detector die.
Analysis Lab

DOWNLOAD

Authored By:


Terry Bowen
TE Connectivity
Harrisburg, PA, USA

Summary


One of the primary technical challenges associated with the manufacture of optical assemblies, especially systems with higher levels of integration, is component to component optical alignment. Components must be brought into precise spatial relationship and the precision of this alignment must be captured and maintained throughout the useful lifetime of the assembly. The alignment step can be done actively or passively. The active approach is more complicated involving powering up devices and measuring optical coupling results while moving the components into the aligned position. The passive approach relies on building precision into the parts so that they can be directly assembled into the aligned position without activating the components.

This paper describes the use of a large Vgroove wet etched into a silicon wafer to form an alignment bench component, which can be used in combinations with silicon based interposer / photonic integrated circuit (PIC) die and either additional similar die, or optical fibers assembled with cylindrical ferrules such as the LC connector ferrule.

The silicon interposer die / PIC die are constructed with wet etched v-grooves along the locations where the die will be diced. This allows the sidewalls of these edge locator grooves to be used in combination with the alignment bench to precisely position features on the die relative to other similarly constructed components or optical fibers. The accuracy achieved by the photolithographic processes employed allow passive alignment to be used for constructing these assemblies.



Conclusions


The use of a Wide Alignment Groove (WAG) that is wet etched from a silicon wafer to form an alignment bench component as been presented. The WAG, is used to align a combination of components such as a Silicon based Interposer (SI) / Photonic Integrated Circuit (PIC) die to either additional similar die, or to cylindrical ferrule connector receptacle sub-assemblies such as the LC connector ferrule receptacle sub-assembly described here. The silicon interposer die / IC die are constructed with wet etched locator v-groove sidewalls along the locations where the die are diced. The sidewalls are used in combination with the WAG to precisely position features on the die relative to features on other similarly constructed die or to optical fibers. The accuracy achieved by the photolithographic processes employed enable passive alignment to be used for the construction of these assemblies.

The Silicon Interposer described provided electrical interconnects to an edge emitting laser die and a laser monitor detector die. The electrical interconnects were formed using an advanced electrical interconnect process developed at MA/COM for their glass microwave integrated circuits (GMIC process). It involved etching pockets into the silicon wafer and then filling the pockets with glass frit material and processing the wafer to produce a surface with areas of glass and areas of silicon. The metallic electrical traces for this SI were run on the glass material areas in order to provide impedance control and dielectric isolation from the silicon substrate. Through Silicon Vias (TSVs)were used to interconnect the top surface pads of the SI to the back surface ground layer in order to provide top surface grounding.

One of the primary technical challenges associated with the manufacture of optical assemblies, especially systems with higher levels of integration, is the component to component optical alignment. The alignment step can be done actively or passively. The active approach is more complicated involving powering up devices and measuring optical coupling results while robotically moving the components into the optimum aligned position. The passive approach as described in this paper, relies on building precision into the parts using wafer scale photolithography. This approach provides component parts that can be directly assembled into the aligned position without activating the components.

Once the components are brought into precise spatial relationship the precision of this alignment is captured and maintained throughout the useful lifetime of the assembly. The resulting assembly provides a chip-to-world interconnect that can be automated to produce high volumes.

Initially Published in the SMTA Proceedings

Comments

No comments have been submitted to date.

Submit A Comment


Comments are reviewed prior to posting. You must include your full name to have your comments posted. We will not post your email address.

Your Name


Your Company
Your E-mail


Your Country
Your Comments



Board Talk
How Effective Is Nano Coating On Stencils?
What Causes Board Delamination?
01005 Component Challenges and Bugs
Sticky Residue Under Low Clearance Parts
Soldering Relays Intrusively in Lead Free Process
Printing vs. Dispensing
Maximum Board Temperature During Tin-Lead
Is There a Spacing Spec for SMD Components?
MORE BOARD TALK
Ask the Experts
HASL vs. Immersion Gold
Very Low Temp PCBs
Looking for Long-term Component Storage Options
Baking After Cleaning Hand Placed Parts
Conformal Coating Recommendation
Burned Chip Repair
BGA Component Grounding Problem
What is the IPC Definition of Uncommonly Harsh?
MORE ASK THE EXPERTS